Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies

Florance, D. Rebecca; Prabhakar, B.

doi:10.1016/j.vlsi.2022.09.002

Cited by 6 publications

(2 citation statements)

References 22 publications

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“…The suggested adder-subtractor module provides 2-bit ternary numbers with addition and subtraction [20]- [23]. The module accomplishes operations using the symmetry idea in a ternary adder and the structure of a subtractor from a popular ternary adder module [24], [25].…”

Section: Adder Subtractor Modulementioning

confidence: 99%

Ternary arithmetic and logic unit with carbon nanotube-based field-effect transistors for ultra-low power and high-speed applications

Krishna Peddachowdappa,

Vardhan

2023

IJEECS

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<span>The number of consumers for different applications has expanded tremendously as a result of the growth of consumer electronics-related applications in numerous sectors. Customers often need high-speed applications that use a minimal amount of power for a variety of applications like signal processing, picture processing, communication systems, and so on. The speed of a ternary logic-based design might be greater than that of a binary logic-based one. In this study, a novel architecture for arithmetic and logic units (ALUs) is proposed. The design makes use of ternary logic. In order to accomplish both low power consumption and high performance, methodologies for designing carbon nanotube-based field-effect transistors (CNTFETs) are employed. The method that has been suggested is able to carry out operations such as addition, subtraction, multiplication, reasoning, and comparison. After developing the recommended model, it is compared to earlier designs for power delay product (PDP), average power consumption, and maximum delay duration. The simulation findings show that the carbon nanotube field effect transistors (CNTFET) based ternary ALU circuits outperformed conventional ternary full adder circuits. The suggested design had a delay time of 13.94 ps and a PDP of 5.32 aJ, while the old design had a delay time of 17.67 ps and a PDP of 51.38 aJ.</span>

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Section: Adder Subtractor Modulementioning

confidence: 99%

Ternary arithmetic and logic unit with carbon nanotube-based field-effect transistors for ultra-low power and high-speed applications

Krishna Peddachowdappa,

Vardhan

2023

IJEECS

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“…CMOS specifications were used to create the basic semiconductor technology that was used to build the traditional adders and subtractors. There is an increase of more transistors and delays because of this [20]. The benefit of traditional CMOS logic is its resistance to voltage scaling, which is necessary for dependable operation at low voltage.…”

Section: Introductionmentioning

confidence: 99%

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Battini

PASHYA

Sivani

2023

Preprint

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Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks such as half adder and excess-1 circuit used in this PCSA is realized using only a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA exhibits better circuit regularity. The new topology of PCSA is designed using FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are designed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL at 18nm FinFET technology. The result analysis reveals that the speed performance and the number of transistors of 8-bit PCSA are better by 44.02% and 4% respectively compared to existing adders.

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1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages

Lakshmanachari,

Shaik,

Satyanarayana

et al. 2023

Int J Syst Assur Eng Manag

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Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies

Cited by 6 publications

References 22 publications

Ternary arithmetic and logic unit with carbon nanotube-based field-effect transistors for ultra-low power and high-speed applications

Ternary arithmetic and logic unit with carbon nanotube-based field-effect transistors for ultra-low power and high-speed applications

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages

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