Intelligent merging online task placement algorithm for partial reconfigurable systems

Marconi, Thomas; Lu, Yi; Bertels, Koen; Gaydadjiev, Georgi

doi:10.1145/1403375.1403699

Cited by 22 publications

(17 citation statements)

References 11 publications

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“…But finding maximum key elements and the MER is time consuming. Marconi et al [15,16] proposed an intelligent merging technique to speed up Bazargan algorithm without losing its placement quality. It is a combination of three techniques selected based on the task characteristics.…”

Section: Related Workmentioning

confidence: 99%

“…In this figure, three tasks 1 , 2 , and 3 are already placed at locations 12, 54, and 24, respectively, on an FPGA of size 8 × 8. The remaining free area can be described using free space run-length matrix as shown below: FRL = {(0, 12) , (16,8) , (32, 16) , (56, 8)} .…”

Section: Proposed Workmentioning

confidence: 99%

“…In the above example, the algorithm finds two positions for placing the incoming task shown as A and B, in Figure 1. For placing at A, we need vacant space (32, 16) and placing at B requires vacant space TRL = { (16,8), (40, 8)}. Based on resulting fragmentation one among these will be selected for placing the incoming task.…”

Section: Proposed Workmentioning

confidence: 99%

See 2 more Smart Citations

An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve

Olakkenghil¹,

Baskaran²

2014

International Journal of Reconfigurable Computing

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With the arrival of partial reconfiguration technology, modern FPGAs support tasks that can be loaded in (removed from) the FPGA individually without interrupting other tasks already running on the same FPGA. Many online task placement algorithms designed for such partially reconfigurable systems have been proposed to provide efficient and fast task placement. A new approach for online placement of modules on reconfigurable devices, by managing the free space using a run-length based representation. This representation allows the algorithm to insert or delete tasks quickly and also to calculate the fragmentation easily. In the proposed FPGA model, the CLBs are numbered according to reflected binary gray space filling curve model. The search algorithm will quickly identify a placement for the incoming task based on first fit mode or a fragmentation aware best fit mode. Simulation experiments indicate that the proposed techniques result in a low ratio of task rejection and high FPGA utilization compared to existing techniques.

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Section: Related Workmentioning

confidence: 99%

Section: Proposed Workmentioning

confidence: 99%

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An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve

Olakkenghil¹,

Baskaran²

2014

International Journal of Reconfigurable Computing

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“…There are lots of studies on how to map applications to PEs on chip based on the communications among small tasks [19][20][21][22][23]. Actually, these studies have few consideration on the I/O requirements of the mapped applications.…”

Section: A Analysis Of Applications On Nocmentioning

confidence: 99%

Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications

Wang

Wen

et al. 2010

2010 10th IEEE International Conference on Computer and Information Technology

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The progress of manufacturing technology makes the integration of many cores on a single silica substrate possible, which is called chip multiprocessor (CMP). But how to design the fabric on chip is still in discussion. Based on the advantages of scalability, network on chip (NoC) is a promising solution to solve the on-chip interconnection problem. However, it is still a challenge when communications through wires dominate the performance. The network communications infrastructure (routing, adapters and wires, etc.) cost too much both in power consumption and die area. In this paper, we propose a novel on-chip structure with dynamic reconfiguration capability for I/O supported parallel application. Our motivation is to reduce the cost of chip areas greatly by dynamic reconfiguration of the network in NoC architecture under the conditions that I/O parallel applications can be supported and the performance can be optimized. In our design, I/O node will be obtained firstly and then the information of the spare processing elements (PE) near it. Finally, combined with the communication pattern of applications, wires will be reallocated and reconfigurated to create a virtual regionalized area. The experimental results show that we can get a certain level of optimization among chip area, communication efficiency and the performance of I/O supported parallel applications.

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“…[2] takes into account the feasibilty of non-preemptive scheduling and feasibility of placement which enhances the success of placement process. In [3], Marconi proposes Intelligent Merging (IM) algorithm which combines dynamically three new techniques: Merging Only if Needed, Partially Merging and Direct Combine. IM speedup the Bazargan algoritm and outperfroms its quality as it accelerates the execution time of placement by 3 times.…”

Section: Introductionmentioning

confidence: 99%

Off-line placement of hardware tasks on FPGA

Belaïd

Muller

Benjemaa

et al. 2009

2009 International Conference on Field Programmable Logic and Applications

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The new tendencies in designing real-time systems indicate that the future applications will be built on reconfigurable hardware devices. These applications require high performance and reasonable flexibility towards user and environment needs. To fulfill these application requirements, the density of heterogeneous resources evolves within these devices. Hence, the complexity of these devices leads to the search of efficient mechanisms to manage hardware resources. The proposed placement methods suffer from issues of fragmentation, tasks rejection, and overheads. This paper focuses on an off-line flow of hardware tasks' classification that aims at the optimized use of the resources and targets all above mentioned issues.

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Intelligent merging online task placement algorithm for partial reconfigurable systems

Cited by 22 publications

References 11 publications

An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve

An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve

Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications

Off-line placement of hardware tasks on FPGA

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