Off-line placement of hardware tasks on FPGA

Abstract

The new tendencies in designing real-time systems indicate that the future applications will be built on reconfigurable hardware devices. These applications require high performance and reasonable flexibility towards user and environment needs. To fulfill these application requirements, the density of heterogeneous resources evolves within these devices. Hence, the complexity of these devices leads to the search of efficient mechanisms to manage hardware resources. The proposed placement methods suffer from issues of fragmentation, tasks rejection, and overheads. This paper focuses on an off-line flow of hardware tasks' classification that aims at the optimized use of the resources and targets all above mentioned issues.

New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA

“…Configuration overhead is determined as described in (7) by considering that each task defines an RZ. After synthesizing hardware tasks by the ISE tool, they are modeled under their RB-model reported in [3]. The partial reconfiguration flow dedicated by the Planahead tool enables the floorplanning of hardware tasks on the chosen device to create their bitstreams independently for estimating configuration overheads.…”

“…The RBs are closely shaped to the reconfiguration granularity in the chosen technology. The determination of the RB-model of hardware tasks is well-detailed in our work in [3]. Each type of RB is characterized by specified cost RBCost k which is defined according to three parameters: the number of the RB type in the device, its power consumption and the importance of its functionality.…”

“…During the conception of three-level resource management, we rely on the physical architecture of target technology and on the advantages of dynamic partial reconfiguration. The contribution of this paper is the development of (i) offline flow for hardware task classification which is an enhancement of our previously proposed work in [3] and which creates task classes, (ii) a formulation of the task placement as a constrained optimization problem and its resolution by powerful solvers using Branch and Bound method by considering two independent sublevels: the first sublevel ensures the fitting of obtained task classes on physical blocs partitioned on target technology which improves resource efficiency up to 36% and the second sublevel performs the mapping of tasks to obtained classes by optimizing the overall overhead up to 11% of total running time and by minimizing the number of task relocations.…”

An FPGA Task Placement Algorithm Using Reflected Binary Gray Space Filling Curve

“…Steiger et al [21][22][23] proposed stuffing techniques for combined placement and scheduling. Belaid et al [24] proposed an offline algorithm for placement of tasks. ELfarag et al [25] and Esmaeildoust et al [26] proposed various fragmentation aware techniques.…”

Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow

“…A design using partial dynamic reconfiguration, as the one provided by Xilinx FPGAs [17], is composed of a static part and defined reconfigurable zones in which reconfigurable modules can be loaded. Using this technology, the operating system is able to schedule hardware threads [18], without resetting the rest of the system. For real-time applications, both readback and reconfiguration overheads must be minimized using a dedicated hardware reconfiguration controller, such as FaRM [19], Uparc [20] or the solution offered by Koch et al [21].…”