Intellectual property core implementation of decision trees

Struharik, Rastislav; Novak, Ladislav A.

doi:10.1049/iet-cdt.2008.0055

Cited by 12 publications

(6 citation statements)

References 6 publications

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“…The architecture for hardware acceleration of sparse decision trees, called SDTA (Sparse Decision Tree Accelerator), is the evolution of SMpL architecture introduced in [24]. Let us consider the DT shown in the Fig.…”

Section: Hardware Accelerator For Sparse Dtsmentioning

confidence: 99%

“…Therefore, to classify an instance, there is no reason to evaluate every node in the DT, but only a selected subset of nodes, one from each DT level, at most. SMpL architecture, originally presented in [24], that evaluates only visited DT nodes during the classification of an instance, is more efficient than the architecture in [22] in terms of separate node modules that need to be implemented in hardware. For example, Fig.…”

Section: Hardware Accelerator For Sparse Dtsmentioning

confidence: 99%

“…The SDTA architecture that we are proposing is explicitly designed to take an advantage of such an optimization. SDTA architecture is closely related to SMpL architecture presented in [24], but modified in order to be able to skip all unnecessary computations due to the fact that some hyperplane coefficients ai becomes equal to zero as a result of the sparsification introduced in each DT node.…”

Section: Hardware Accelerator For Sparse Dtsmentioning

confidence: 99%

“…Compared to SMpL architecture from [24], the node processing time of the SDTA architecture is measured in clock cycles, equals:…”

Section: Hardware Accelerator For Sparse Dtsmentioning

confidence: 99%

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Hardware Acceleration of Sparse Oblique Decision Trees for Edge Computing

Teodorovic¹,

Struharik²

2019

ELEKTRON ELEKTROTECH

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This paper presents a hardware accelerator for sparse decision trees intended for FPGA applications. To the best of authors’ knowledge, this is the first accelerator of this type. Beside the hardware accelerator itself, a novel algorithm for induction of sparse decision trees is also presented. Sparse decision trees can be attractive because they require less memory resources and can be more efficiently processed using specialized hardware compared to traditional oblique decision trees. This can be of significant interest, particularly, in the edge-based applications, where memory and compute resources as well as power consumption are severely constrained. The performance of the proposed sparse decision tree induction algorithm as well as developed hardware accelerator are studied using standard benchmark datasets obtained from the UCI Machine Learning Repository database. The results of the experimental study indicate that the proposed algorithm and hardware accelerator are very favourably compared with some of the existing solutions.

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Section: Hardware Accelerator For Sparse Dtsmentioning

confidence: 99%

Section: Hardware Accelerator For Sparse Dtsmentioning

confidence: 99%

Section: Hardware Accelerator For Sparse Dtsmentioning

confidence: 99%

“…Compared to SMpL architecture from [24], the node processing time of the SDTA architecture is measured in clock cycles, equals:…”

Section: Hardware Accelerator For Sparse Dtsmentioning

confidence: 99%

See 2 more Smart Citations

Hardware Acceleration of Sparse Oblique Decision Trees for Edge Computing

Teodorovic¹,

Struharik²

2019

ELEKTRON ELEKTROTECH

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“…The disadvantage of this approach is large latency, due to the fact that a new test pattern cannot be fed into the module before the classification output has propagated. To overcome the large latency problem, a universal node DT architecture [ Figure 2(b)], using registers to pipeline each stage, was proposed in [14]. Although it reduces hardware cost by folding each level, it exhibits a relatively low throughput as a result of serial processing [13,14].…”

Section: Hardware Considerationsmentioning

confidence: 99%

A Low-Power Hardware-Friendly Binary Decision Tree Classifier for Gas Identification

Bermak

2011

JLPEA

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In this paper, we present a hardware friendly binary decision tree (DT) classifier for gas identification. The DT classifier is based on an axis-parallel decision tree implemented as threshold networks-one layer of threshold logic units (TLUs) followed by a programmable binary tree implemented using combinational logic circuits. The proposed DT classifier circuit removes the need for multiplication operation enabling up to 80% savings in terms of silicon area and power compared to oblique based-DT while achieving 91.36% classification accuracy without throughput degradation. The circuit was designed in 0.18 µm Charter CMOS process and tested using a data set acquired with in-house fabricated tin-oxide gas sensors.

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