Parameterizable Decision Tree Classifier on NetFPGA

Monemi, Alireza; Zarei, Roozbeh; Marsono, Muhammad Nadzir; Khalil-Hani, Mohamed

doi:10.1007/978-3-642-32063-7_14

Cited by 4 publications

(1 citation statement)

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“…It cannot handle general classifier using flow-level features. [15] proposes a hardware architecture on NetFPGA for decision tree based classifier. Their architecture is fully parameterizable in terms of throughput, number of features, tree depth and maximum number of nodes with in a tree level.…”

Section: Fpga Based Traffic Classifiermentioning

confidence: 99%

High throughput and programmable online trafficclassifier on FPGA

Tong

Sun

Matam

et al. 2013

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Machine learning (ML) algorithms have been shown to be effective in classifying the dynamic internet traffic today. Using additional features and sophisticated ML techniques can improve accuracy and can classify a broad range of application classes. Realizing such classifiers to meet high data rates is challenging. In this paper, we propose two architectures to realize complete online traffic classifier using flowlevel features. First, we develop a traffic classifier based on C4.5 decision tree algorithm and Entropy-MDL discretization algorithm. It achieves an accuracy of 97.92% when classifying a traffic trace consisting of eight application classes. Next, we accelerate our classifier using two architectures on FPGA. One architecture stores the classifier in on-chip distributed RAM. It is designed to sustain a high throughput. The other architecture stores the classifier in block RAM. It is designed to operate with small hardware footprint and thus built at low hardware cost. Experimental results show that our high throughput architecture can sustain a throughput of 550 Gbps assuming 40 Byte packet size. Our low cost architecture demonstrates a 22% better resource efficiency than the high throughput design. It can be easily replicated to achieve 449 Gbps while supporting 160 input traffic streams concurrently. Both architectures are parameterizable and programmable to support any binary-tree-based traffic classifier. We develop a tool which allows users to easily map a binary-tree-based classifier to hardware. The tool takes a classifier as input and automatically generates the Verilog code for the corresponding hardware architecture.

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Section: Fpga Based Traffic Classifiermentioning

confidence: 99%