Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

Sell, B.; An, S.; Armstrong, Jeffrey L.; Bahr, David F.; Bains, Balijeet; Bambery, R.; Bang, K.; Basu, Dipanjan; Bendapudi, S.; Bergstrom, D.; Bhandavat, R.; Bhowmick, S.; Buehler, Markus J.; Caselli, D.; Cekli, S.; Chaganti, Vrsk.; Chang, Yin-Jung; Chikkadi, K.; Chu, T.; Crimmins, Timothy F.; Darby, Greg; Ege, Canay; Elfick, P.; Elko-Hansen, T.; Fang, Sheng-Po; Gaddam, C.; Ghoneim, M.; Gomez, Hector; Govindaraju, Sridhar; Guo, Z.; Hafez, W.; Haran, Michael E.; Hattendorf, M.; Hu, Shiliang; Jain, Abhishek; Jaloviar, S.; Jang, M.; Kameswaran, J.; Kapinus, V.; Kennedy, A.; Klopčič, Sabina Beranič; Krishnan, D.; Leib, J.; Lin, Yutien; Lindert, N.; Liu, G.; Loh, O.; Luo, Yuxuan; Mani, S.; Mleczko, M.; Mocherla, S.; Packan, P.; Paik, M.; Paliwal, Ayushi; Pandey, R.; Patankar, K.; Pipes, Leonard C.; Plekhanov, P. S.; Prasad, C.; Prince, M.; Ramalingam, G.; Ramaswamy, R.; Riley, Jr. R.L.; Perez, Jose Roberto Sanchez; Sandford, J.; Sathe, A.; Shah, F.; Shim, Hyoeun; Subramanian, Srinath; Tandon, Shalabh; Tanniru, M.; Thakurta, Dipto G.; Troeger, T.; Wang, X.; Ward, C.; Welsh, Alex; Wickramaratne, S.; Wnuk, Joshua D.; Xu, Shengbo; Yashar, P.; Yaung, J.; Yoon, Kyung Jean; Young, N.

doi:10.1109/vlsitechnologyandcir46769.2022.9830194

Cited by 16 publications

(5 citation statements)

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“…22 Since the subsequent process for N-FETs inevitably degrades the fabricated P-FETs, both N-and P-FETs in CMOS will be inferior to the solely fabricated N-and P-FETs, which is the compromise in CMOS technologies. Moreover, compared with the performance of the advanced technology node of silicon like "intel 4", 1 there also exists a certain distance between A-CNTs and silicon. So, the obvious performance difference between A-CNT CMOS FETs and the solely built P-FETs (or N-FETs) and even silicon CMOS FETs at the advanced technology node indicates that there is still enough room to improve our CMOS technology through further optimizing the fabrication process.…”

Section: Resultsmentioning

confidence: 99%

“…A s the mainstream integrated circuit (IC) technology, silicon-based complementary metal-oxide−semiconductor (CMOS) technology is entering the sub-5 nm node regime, and further development is facing increasing challenges from the physical, technological, and cost aspects. 1,2 Technological changes in fundamental devices (physical level) or computing architectures (system level) are highly desired and extensively explored to meet the ever-increasing demand for ICs. 3−5 At the physical level, an enormous amount of research effort is aimed at finding a semiconductor as a substitute for Si to construct transistors with increased performance and decreased power dissipation and cost.…”

mentioning

confidence: 99%

“…As the mainstream integrated circuit (IC) technology, silicon-based complementary metal-oxide–semiconductor (CMOS) technology is entering the sub-5 nm node regime, and further development is facing increasing challenges from the physical, technological, and cost aspects. , Technological changes in fundamental devices (physical level) or computing architectures (system level) are highly desired and extensively explored to meet the ever-increasing demand for ICs. − At the physical level, an enormous amount of research effort is aimed at finding a semiconductor as a substitute for Si to construct transistors with increased performance and decreased power dissipation and cost. − Therefore, low-dimensional semiconductors with ultrathin bodies and high carrier mobilities have attracted increasing attention. − The ultrathin body brings intrinsic immunity to short channel effects and excellent scaling behavior with a low-cost planar manufacturing process, while the high carrier mobility provides the potential for high performance for scaled transistors. Furthermore, the success of Si IC technology shows that CMOS field-effect transistors (FETs) are necessary for candidate IC technology to provide low power dissipation and high noise margin. − …”

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confidence: 99%

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Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays

et al. 2022

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High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been demonstrated with wafer-scale preparation of materials and have shown high performance in P-type field-effect transistors (FETs) and great potential for applications in future digital integrated circuits (ICs). However, high-performance N-type FETs (N-FETs) have not yet been implemented with A-CNTs, making development of complementary metal-oxide−semiconductor (CMOS) technology, a necessary component for modern digital ICs, impossible. In this work, we reveal the mechanism hindering the realization of A-CNT N-FETs contacted by low-work-function metals and develop corresponding solutions to promote the performance of N-FETs to that of P-type FETs (P-FETs). The fabricated scandium (Sc)-contacted A-CNT N-FET with a 100 nm gate length exhibits an on-state current (I on ) of 800 μA/μm and a peak transconductance (g m ) of 250 μS/μm, representing the highest performance of CNT-based N-FETs to date. Moreover, CMOS technology has been developed to realize N-and P-FETs with symmetric high performance based on A-CNTs. The fabricated A-CNT CMOS FETs show electron and hole mobilities of 325 and 241 cm 2 V −1 s −1 , respectively, which are slightly higher than the corresponding values of Si CMOS transistors. Our scalable fabrication of A-CNT CMOS FETs with comparable electronic performance to Si CMOS will promote the application of CNT-based electronics in digital ICs.

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Section: Resultsmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays

et al. 2022

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“…Extreme ultraviolet (EUV) lithography has been adopted for 3D technology, which has increasing numbers of passes, in high volume manufacturing of 7- and 5-nm node logic integrated circuits and 16/14-nm node DRAM 8 – 10 Compared with 193-nm immersion lithography, EUV lithography enhances resolution, reduces the number of lithographic passes for critical device levels, improves pattern fidelity and reduces manufacturing cost when adopted appropriately. Recently a new EUV resist technology was developed, where both the resist deposition and the resist development can be conducted in a dry gaseous phase.…”

Section: Introductionmentioning

confidence: 99%

Probing molecular structures at buried solid/solid interfaces involving low-k materials or polymers in situ nondestructively: a review

Zhang

Chen

2023

J. Micro/Nanopattern. Mats. Metro.

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Background: With the development of three-dimensional (3D) integration technology including extreme ultraviolet (EUV) lithography, more and more buried interfaces are involved in a device. It is important to probe such buried solid/solid interfaces in situ, but due to the lack of appropriate metrology, it is difficult to do so.Aim: This review aims to introduce sum frequency generation (SFG) vibrational spectroscopy to researchers and engineers in the research fields related to 3D integration technology including EUV lithography. SFG can probe buried solid/solid interfaces in situ nondestructively.Review Approach: This review presents the SFG technique and the recent results obtained from SFG studies on a variety of solid/solid interfaces, including porous low-k material/silicon interfaces, plasma treated polymer/epoxy interfaces, flux treated metal/epoxy interfaces, chemical reactions at buried solid/solid interfaces, and structures of buried solid/solid interfaces in multilayered thick device.Conclusions: SFG has been successfully applied to elucidate molecular structures and molecular interactions at buried solid/solid interfaces in situ nondestructively. SFG has great potential to probe buried interfaces in devices based on 3D integration technology.

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“…Eventually, this long-term scaling reached tremendous difficulties due to short channel effects, such as drain induced barrier lowering [1]. One approach to mitigate short channel effects are FinFET devices [2], which were successfully scaled down to the sub 22 nm regime. Recently, leading semiconductor companies like IBM introduced the 2 nm technology node, with a typical gate length of 14 nm and a 44 nm pitch.…”

Section: Introductionmentioning

confidence: 99%

Buried graphene heterostructures for electrostatic doping of low-dimensional materials

et al. 2023

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The fabrication and characterization of steep slope transistor devices based on low-dimensional materials requires precise electrostatic doping profiles with steep spatial gradients in order to maintain maximum control over the channel. In this proof-of-concept study we present a versatile graphene heterostructure platform with three buried individually addressable gate electrodes. The platform is based on a vertical stack of embedded titanium and graphene separated by an intermediate oxide to provide an almost planar surface. We demonstrate the functionality and advantages of the platform by exploring transfer and output characteristics at different temperatures of carbon nanotube field-effect transistors with different electrostatic doping configurations. Furthermore, we back up the concept with finite element simulations to investigate the surface potential. The presented heterostructure is an ideal platform for analysis of electrostatic doping of low-dimensional materials for novel low-power transistor devices.

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Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

Cited by 16 publications

References 1 publication

Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays

Complementary Transistors Based on Aligned Semiconducting Carbon Nanotube Arrays

Probing molecular structures at buried solid/solid interfaces involving low-k materials or polymers in situ nondestructively: a review

Buried graphene heterostructures for electrostatic doping of low-dimensional materials

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