Integration and reliability issues for low capacitance air-gap interconnect structures

Shieh, B.; Bassman, Lori; Kim, D.-K.; Saraswat, Krishna C.; Deal, Michael D.; McVittie, J.P.; List, R. S.; Nag, Somnath; Ting, Larry

doi:10.1109/iitc.1998.704769

Cited by 15 publications

(9 citation statements)

References 3 publications

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“…Several processing techniques have been disclosed for forming air-isolation in electronic devices including the use of CMP and via etch [4], etch back technique [7][8], sacrificial polymers [5,6,[10][11][12][13], and wet etching [9]. Among these techniques, the use of a sacrificial polymer for creation of air-gaps is a promising method which can be applied to a variety of applications.…”

Section: Fabrication Of Air-gap Structuresmentioning

confidence: 99%

“…These include thermal reliability [4], electromigration reliability [14][15], dielectric reliability [16], process induced stresses [17], moisture uptake, and corrosion of metal wiring [18]. The fabrication of air-gap structure also requires a careful look at the mechanical stability of the structures.…”

Section: Fabrication Of Air-gap Structuresmentioning

confidence: 99%

“…Denoting the relative permittivity of the overcoat as ε r , the effective permittivity ranges in the suspended and inverted air-gap horizontal lines are given in Equation 4 [24]. 1 (4) Thus, the diminishing effective permittivity in inverted air-gap lines will decrease the dielectric loss and improve the signal integrity. Figure 14 summarizes the concept of a horizontal inverted air-gap differential transmission line structure.…”

Section: Technology Improvement In the Air-gap Interconnect Linesmentioning

confidence: 99%

“…Previous reports have explored the role of air-gap structures in lowering line capacitance [3][4][5][6][7][8][9]. When depositing SiO 2 , air-gaps or voids can be formed between metal lines.…”

Section: Background 21 Capacitance Reduction Using Air Gap Structuresmentioning

confidence: 99%

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Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Uzunlar

Sharma

Saha

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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In this study, we are pursuing an ultra low-loss interconnect pathway for 3D chip-chip connectivity, incorporating air-clad planar interconnects, air-clad TSVs, and gradual vertical-horizontal transitions. The motivation is to create an air-gap technology that offers the lowest possible effective k-value and near zero loss tangent minimizing the dielectric loss. The design and modeling of air-gap interconnection is presented. The fabrication challenges in airclad interconnect lines are discussed. A monolithic inverted air-gap horizontal transmission line structure is proposed as a means for further decreasing the dielectric loss. Extension of air-clad TSV technology for optical transmission is briefly discussed. IntroductionModern electronic systems are composed of a dense fabric of interconnect lines that connect electronic devices and chips. The scaling of transistors has resulted in miniaturization of individual devices and their interconnects. Smaller crosssectional area of electrical interconnects results in higher signal attenuation and makes data and clock recovery complex. High-speed interconnects have two primary loss mechanisms, namely metallic skin effect losses and dielectric losses. Skin effect loss is a phenomenon where, at high frequencies, the current is crowded into the near-surface region of the metal around the periphery of the conductor. As a result, the effective AC resistance per unit length of conductor increases with frequency. The second loss mechanism deals with dielectric losses. Dielectric losses are directly proportional to frequency and are therefore more pronounced at higher frequencies. Also, resistive losses in the return ground path cannot be ignored and are determined by the geometry and materials constituting the return path. Overall, dielectric losses dominate at frequencies above several GHz [1-2], as shown in Figure 1. This figure was produced with data from the International Technology Roadmap for Semiconductors (ITRS) for signal frequencies up to 50 GHz. As shown in Figure 1, the dielectric loss is more than twice that of the conductor loss at 20 GHz and the dielectric loss becomes more dominant at frequencies above 20 GHz. Thus, in order to achieve meaningful reduction in signal attenuation it is important to find ways to mitigate the dielectric loss at high frequencies. One way of achieving this goal is to use better interconnect and substrate materials.

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Section: Fabrication Of Air-gap Structuresmentioning

confidence: 99%

Section: Fabrication Of Air-gap Structuresmentioning

confidence: 99%

Section: Technology Improvement In the Air-gap Interconnect Linesmentioning

confidence: 99%

Section: Background 21 Capacitance Reduction Using Air Gap Structuresmentioning

confidence: 99%

See 2 more Smart Citations

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Uzunlar

Sharma

Saha

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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show abstract

“…O NE of the biggest challenges for very large-scale integration (VLSI) technology is the ac power consumption [1] caused by the interconnect parasitic capacitance ( ), which becomes a major limit for VLSI ICs beyond the implementation of metal-gates and high-nano-CMOS to solve the dc power in gate leakage [2]. Increasing operational frequency ( ) of circuits with denser interconnects makes the ac power consumption even worse.…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices

Chin

Liao

et al. 2005

IEEE Electron Device Lett.

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We demonstrate three-dimensional (3-D) self-aligned [IrO 2 -IrO 2 -Hf]-LaAlO 3 -Ge-on-Insulator (GOI) CMOSFETs above 0.18-m Si CMOSFETs for the first time. At an equivalent oxide thickness of 1.4 nm, the 3-D IrO 2 -LaAlO 3 -GOI p-MOSFETs and IrO 2 -Hf-LaAlO 3 -GOI nMOSFETs show high hole and electron mobilities of 234 and 357 cm 2 Vs respectively, without depredating the underneath 0.18-m Si devices. The hole mobility is 2.5 times higher than the universal mobility, at 1 MV/cm effective electric field. These promising results are due to the low-temperature GOI device process, which is well-matched to the low thermal budget requirements of 3-D integration. The high-performance GOI devices and simple 3-D integration process, compatible to current very large-scale integration (VLSI) technology, should be useful for future VLSI. Index Terms-Ge-on-insulator (GOI), LaAlO 3 , metal-gate, MOSFET, three-dimensional (3-D).

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Compact quasi-analytic equations for estimating the temperature distribution of ULSI interconnections

Xiao¹,

You²,

Ruan³

2002

Microelectronic Engineering

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Integration and reliability issues for low capacitance air-gap interconnect structures

Cited by 15 publications

References 3 publications

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices

Compact quasi-analytic equations for estimating the temperature distribution of ULSI interconnections

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