Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

Cadix, L.; Rousseau, M.; Fuchs, C.; Leduc, P.; Thuaire, Aurélie; Farhane, R. El; Chaabouni, H.; Anciant, R.; Huguenin, J.-L.; Coudrain, P.; Farcy, A.; Bermond, C.; Sillon, N.; Flechet, B.; Ancey, P.

doi:10.1109/iitc.2010.5510728

Cited by 21 publications

(6 citation statements)

References 2 publications

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“…11 presents simulation results of the total 3D asynchronous link, under typical conditions (Vdd=1.2V, Vcc=0.6V). Typical TSV capacitance was assumed [9], and the switches sized accordingly. This back and forth conversion to single TSV ternary adds two delays to a regular QDI data transfer: 250ps from Ai to Ao (or Bi to Bo) and 360ps from Acko to Acki, in typical conditions.…”

Section: Transmittermentioning

confidence: 99%

A single TSV-rail 3D quasi delay insensitive asynchronous signaling

Belleville

Beigné

Valentian

2011

2011 IEEE International Conference on IC Design &Amp; Technology

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Asynchronous communications are foreseen as mandatory for implementing 3D multiple tiers circuits. The drawback of asynchronous rails compared to synchronous ones is the higher number of interconnects. This number needs to be decreased when horizontal interconnects are replaced by Through Silicon Vias (TSV) because of their big silicon footprint. A circuit using only one TSV for asynchronous, quasi delay insensitive 3D signal propagation is proposed. This achieves to save two TSVs out of three, while offering 1Gbits/s capability.

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Section: Transmittermentioning

confidence: 99%

A single TSV-rail 3D quasi delay insensitive asynchronous signaling

Belleville

Beigné

Valentian

2011

2011 IEEE International Conference on IC Design &Amp; Technology

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“…In this paper, we integrate circuit-level P-SN estimation, system level thermal evaluation and workload assignment together effectively. Our contributions are listed as follows: [10] consider both PSN effect and thermal issue for 3D MPSoCs from the workload assignment perspective.…”

Section: Introductionmentioning

confidence: 99%

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration

Cheng

Todri‐Sanial

Bosio

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogeneous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noises (PSN) for 3D MPSoCs, which can increase critical path delay, and degrade chip performance and reliability. Meanwhile, thermal gradient should also be considered for 3D MPSoCs to avoid hot spots. In the paper, we investigate the PSN effects of different workloads and propose an effective PSN estimation method. Then, a heuristic workload assignment algorithm is proposed to suppress PSN under the given thermal constraint. The experimental results show that PSNs can be reduced significantly compared with thermal-balanced workload assignment scheme, and the system performance can be improved as well.

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“…Furthermore, Si interposer technology is facing some challenges with regard to thermal mechanical reliability and electrical reliability [15][16][17]. One of the key concerns with regard the electrical reliability is the TSV leakage current, which causes excess Joule heat and unexpected RC paths (leading to subsequent thermal issues and signal delay) [18].…”

Section: Introductionmentioning

confidence: 99%

Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current

Luo

Wang

Sun

et al. 2018

J. Micromech. Microeng.

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The application of a Si interposer is hindered by its complicated manufacturing process, high cost and some reliability challenges such as through silicon via (TSV) leakage. In this paper, a fabrication approach using a Si interposer is proposed, which can simplify the manufacturing process significantly and reduce the cost by more than 40%. Benefiting from the simplified process, the TSV insulation layer stays intact during the whole manufacturing process, an ultra-low TSV leakage current can be obtained. To evaluate the performance and reliability of the interposer, test samples consisting of 136 TSVs are designed and fabricated. A series of tests are carried out to verify the electrical insulating performance and reliability of the interposer. Under the bias voltage of 5 V, the TSV leakage current is 2.05 × 10−14 A, which is much lower than the usual value in the range of 10−12–10−9 A. The yield of daisy chains exceeds 91.66% and that of individual TSVs is more than 99.91%. All the interposer samples have successfully passed the thermal cycle test, and the resistance variation of each individual pathway is within 5% after 200 cycles.

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Integration and frequency dependent electrical modeling of Through Silicon Vias (TSV) for high density 3DICs

Cited by 21 publications

References 2 publications

A single TSV-rail 3D quasi delay insensitive asynchronous signaling

A single TSV-rail 3D quasi delay insensitive asynchronous signaling

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration

Fabrication and characterization of a low-cost interposer with an intact insulation layer and ultra-low TSV leakage current

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