Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration

Abstract

In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogeneous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noises (PSN) for 3D MPSoCs, which can increase critical path delay, and degrade chip performance and reliability. Meanwhile, thermal gradient should also be considered for 3D MPSoCs to avoid hot spots. In the paper, we investigate the PSN effects of different workloads and propose an effective PSN estimation method. Then, a heuristic workload assignment algorithm is proposed to suppress PSN under the given thermal constraint. The experimental results show that PSNs can be reduced significantly compared with thermal-balanced workload assignment scheme, and the system performance can be improved as well.

Intra- and inter-chip voltage droop analysis using a power delivery grid model

“…To analyze the voltage variation, we utilize SPICE for simulation. The synthetic current profiles that represent the core workloads are referred to [2] and the NoC benchmarks are generated from mesh CMP simulator ALPHA. For high and low activities of the workloads, the current profiles are shown respectively in Figure 5.…”

“…Each current source represents the running core with varying activity, and is parallel with a decoupling capacitor. The values of resistance, inductance and capacitance in the power delivery model are referred from [1] [2]. …”

Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint

“…Illustration of the on-chip PDN model [27]. Then, the task scheduling problem can be formulated as follows, min.…”