Integrating thermocouple sensors into 3D ICs

Li, Dawei; Kim, Jihoon; Memik, Seda Öǧrenci

doi:10.1109/iccd.2013.6657046

Cited by 8 publications

(2 citation statements)

References 29 publications

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“…The two layers are connected by a TSV array consists of 32 TSVs (4 × 8 array), in total, as shown in Figure 13. The radius of each TSV is 10μm, the insulation linear thickness is 1μm, and the space between two adjacent TSVs is 30μm, for nowadays, there are many works focusing on TSV models with the TSV radius at 10 micron level or even larger [Lu et al 2009;Ni et al 2010;Li et al 2013]. It should be pointed out that for TSV radius size, this is just for illustration purposes of the proposed analysis algorithm.…”

Section: Numerical Results and Discussionmentioning

confidence: 97%

H -Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICs

Chen

Tan

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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In this article, we propose an efficient finite-element-based (FE-based) method for both steady and transient thermal analyses of high-performance integrated circuits based on the hierarchical matrix (H-matrix) representation. H-matrix has been shown to provide a data-sparse way to approximate the matrices and their inverses with almost linear-space and time complexities. In this work, we apply the H-matrix concept for solving heating diffusion problems modeled by parabolic partial differential equations (PDEs) based on the finite element method. We show that the matrix from a FE-based steady and transient thermal analysis can be represented by H-matrix without any approximation, and its inverse and Cholesky factors can be evaluated by H-matrix with controlled accuracy. We then show and prove that the memory and time complexities of the solver are bounded by O(k 1 N log N) and O(k 2 1 N log 2 N), respectively, where k 1 is a small quantity determined by accuracy requirements and N is the number of unknowns in the system. The comparison with existing product-quality LU solvers, CSPARSE and UMFPACK, on a number of 3D IC thermal matrices, shows that the new method is much more memory efficient than these methods, which however prevents CPU time comparison with those methods on large examples. But the proposed method can solve all the given thermal circuits with decent scalabilities, which shows good agreement with the predicted theoretical results. . 2015. H-matrix-based finite-element-based thermal analysis for 3d ICs.

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Section: Numerical Results and Discussionmentioning

confidence: 97%

H -Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICs

Chen

Tan

et al. 2015

ACM Trans. Des. Autom. Electron. Syst.

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“…The two prominent factors that have contributed to the thermal issues of 3D-ICs are: (i) The high effective power density resulting from multiple overlapping high power density blocks; (i) Multiple chip layers in the vertical direction increasing the total thermal resistance in the path of heat transfer from the chip to the heatsink. Various attempts are made, such as repositioning processor dies to avoid overlapping hotspots, using microfluidic channels, thermal vias, and thermoelectric devices for better heat transfer [11][12][13][14][15]. Still, thermal management of 3D ICs has many problems to tackle.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

Zhang

Guliani

et al. 2017

Proceedings of the 54th Annual Design Automation Conference 2017

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We describe an adaptive thermal management system for 3D-ICs with stacked DRAM cache memories. We present a detailed analysis of the impact of 3D-IC hotspot aggregation on the refresh behavior of the stacked DRAM-based L3 cache. We also present the consequence of the refresh variation on the overall system performance and cache energy consumption. Our analysis demonstrates that memory intensive applications are influenced more strongly by the DRAM refresh variation. We show that there is an optimal operating point where, with a reduced clock frequency, processor cores would actually recover any performance loss induced by DRAM refresh and at the same time the cache energy consumption could be optimized. We propose a low overhead run-time method that can identify the best CPU frequency modulation factor to cool the system to minimize accelerated refresh rates in the DRAM caches. Our system can provide a customizable trade-off between performance of the processor and energy savings of the memory.

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Fabrication and Traceable Quality Evaluation of Fine Pitch TSV with Self-Integrated Micro Heater and Thermocouple

Guan

Zhu

et al. 2016

2016 IEEE 66th Electronic Components and Technology Conference (ECTC)

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Integrating thermocouple sensors into 3D ICs

Cited by 8 publications

References 29 publications

H -Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICs

H -Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICs

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches

Fabrication and Traceable Quality Evaluation of Fine Pitch TSV with Self-Integrated Micro Heater and Thermocouple

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