2008
DOI: 10.1016/j.parco.2008.08.003
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Integrating FPGA acceleration into HMMer

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Cited by 31 publications
(16 citation statements)
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“…Automatic generation of systolic arrays to implement pipelined evaluation of uniform and affine recurrence equations 9 have been studied and found to give significant speedup for many problems. Numerous accelerators for HMMER and Smith-Waterman exist for which the evaluation time is decreased via a combination of architectural improvements, 8,[10][11][12] data path redesign, [13][14][15][16][17][18] and heuristics. 19,20 To our best knowledge, none of the accelerators mentioned above do rely exclusively on algorithmic improvement techniques as we do.…”
Section: Discussion and Related Workmentioning
confidence: 99%
“…Automatic generation of systolic arrays to implement pipelined evaluation of uniform and affine recurrence equations 9 have been studied and found to give significant speedup for many problems. Numerous accelerators for HMMER and Smith-Waterman exist for which the evaluation time is decreased via a combination of architectural improvements, 8,[10][11][12] data path redesign, [13][14][15][16][17][18] and heuristics. 19,20 To our best knowledge, none of the accelerators mentioned above do rely exclusively on algorithmic improvement techniques as we do.…”
Section: Discussion and Related Workmentioning
confidence: 99%
“…In [70], an FPGA implementation of HMMER is investigated. As in HMMERCELL, the computationally intensive kernel of the Viterbi algorithm is the main focus.…”
Section: Hmmer Implementationsmentioning
confidence: 99%
“…Oliver, et al analyzes the feedback loop (J state) and find out it hinder computing one query in parallel [14]. Instead, they parallelize the design at coarse-grained level that is running several independent query sequences at one time, which also accelerates the task of search in overall running time.…”
Section: Related Workmentioning
confidence: 99%
“…Our approach is simpler: our design can dynamically decide the operation of processing elements (PEs) and parallelize the calculations that don't involve the feedback loop; the states number of Plan7 HMM can be assigned at start up. The work in [8] combines both MPI [7] and FPGA [14] strategies together, and the proposed multi-grained acceleration achieves a reasonable speed-up.…”
Section: Related Workmentioning
confidence: 99%
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