Integrating Epitaxial-Like Pb(Zr,Ti)O3 Thin-Film into Silicon for Next-Generation Ferroelectric Field-Effect Transistor

Abstract

The development of ferroelectric random-access memory (FeRAM) technology with control of grain boundaries would result in a breakthrough for new nonvolatile memory devices. The excellent piezoelectric and electrical properties of bulk ferroelectrics are degraded when the ferroelectric is processed into thin films because the grain boundaries then form randomly. Controlling the nature of nucleation and growth are the keys to achieving a good crystalline thin-film. However, the sought after high-quality ferroelectric thin-film has so far been thought to be impossible to make, and research has been restricted to atomic-layer deposition which is extremely expensive and has poor reproducibility. Here we demonstrate a novel epitaxial-like growth technique to achieve extremely uniform and large rectangular-shaped grains in thin-film ferroelectrics by dividing the nucleation and growth phases. With this technique, it is possible to achieve 100-μm large uniform grains, even made available on Si, which is large enough to fabricate a field-effect transistor in each grain. The electrical and reliability test results, including endurance and retention test results, were superior to other FeRAMs reported so far and thus the results presented here constitute the first step toward the development of FeRAM using epitaxial-like ferroelectric thin-films.

Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation

“…The ever-increasing demand for faster CMOS electronics, optoelectronics, and photonic devices has driven a widespread search for next-generation thermal-guiding (TG) structures. TG structures, based on the selective guiding of thermal diffusion around, as well as into, a target region of a TG matrix, , are generally capable of not only steering heat away from critical nodes of integrated circuits (or silicon/chalcogenide devices) to construct higher density, and smaller, transistor devices , but also, more recently, able to direct heat toward key regions of silicon (or chalcogenide) devices to perform multiple, advanced circuit functions, such as Boolean-logic computations and brain-like (neuromorphic) computing. , However, these TG systems are usually large; for example, in integrated circuits, TG structures in the form of heat spreaders and heat sinks are typically on the order of square millimeters, , while, in silicon/chalcogenide devices, TG structures are usually comprised of several hundred nanometers thick insulating layers. , A difficulty arises from the trade-off between increasing (or reducing) the rate of heat transfer and, at the same time, decreasing the contact area to avoid the challenges of integrating these architectures into high-density CMOS circuits …”

“…5,6 However, these TG systems are usually large; for example, in integrated circuits, TG structures in the form of heat spreaders and heat sinks are typically on the order of square millimeters, 7,8 while in silicon/chalcogenide devices, TG structures are usually comprised of several hundred-nanometers-thick insulating layers. 9,10 . A difficulty arises from the trade-off between increasing (or reducing) the rate of heat transfer, and, at the same time, decreasing the contact area to avoid the challenges of integrating these architectures into high-density CMOS circuits.…”