Integrated CPU Cache Power Management in Multiple Clock Domain Processors

Abstract

Abstract. Multiple clock domain (MCD) chip design addresses the problem of increasing clock skew in different chip units. Importantly, MCD design offers an opportunity for fine grain power/energy management of the components in each clock domain with dynamic voltage scaling (DVS). In this paper, we propose and evaluate a novel integrated DVS approach to synergistically manage the energy of chip components in different clock domains. We focus on embedded processors where core and L2 cache domains are the major energy consumers. We propose a policy that adapts clock speed and voltage in both domains based on each domain's workload and the workload experienced by the other domain. In our approach, the DVS policy detects and accounts for the effect of inter-domain interactions. Based on the interaction between the two domains, we select an appropriate clock speed and voltage that optimizes the energy of the entire chip. For the Mibench benchmarks, our policy achieves an average improvement over nopower-management of 15.5% in energy-delay product and 19% in energy savings. In comparison to a traditional DVS policy for MCD design that manages domains independently, our policy achieves an 3.5% average improvement in energy-delay and 4% less energy, with a negligible 1% decrease in performance. We also show that an integrated DVS policy for MCD design with two domains is more energy efficient for simple embedded processors than high-end ones.

Energy Management for Microprocessor Systems: Challenges and Existing Solutions

“…Previous studies use DVS/DFS, multithreaded or multi-core process migration to reduce thermals. AbouGhazaleh et al [14] proposed an integrated DVS approach to synergistically manage the energy of chip components in different clock domains. The proposed policy adapts clock speed and voltage in both domains based on each domain's workload and the workload experienced by the other domain.…”

Towards Dynamic Voltage/Frequency Scaling for Power Reduction in Data Centers

“…As processors consume a large portion of power in computer systems, it is instinctive to reduce power consumptions of processors. AbouGhazaleh et al [14] proposed an integrated DVS approach to synergistically manage the energy of chip components in different clock domains. Lin et al [15] proposed User-Driven Frequency Scaling (UDFS) and Process-Driven Voltage Scaling (PDVS) that can be readily employed independently or together for energy management.…”

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

“…Such paradigm introduces multiple clock domains and accommodates cores and/or IPs to operate at different frequencies while in a single system. Multiple clock domains are also widely effective not only for implementing different functional blocks but also for power management and energyefficient system design [6].…”