Integrated charge pumps: a generalised method for power efficiency optimisation

Cabrini, A.; Gregori, Stefano; Torelli, G.

doi:10.1049/iet-cds.2014.0185

Cited by 8 publications

(7 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In past, the SC-CP operation has been rigorously analyzed [7,8,[10][11][12][13] to accurately predict the CP initial transients and its steady-state response, for a given set of design parameters (CP topology, N , C P , C L ) and specified operating conditions for load current and switching frequency. Such analyses is also utilized to achieve most optimized SC-CP implementation for given set of design specifications, while also assist in understanding the theoretical limits of a given CP topology in terms of CP FOMs.…”

Section: Operational Analysis Of Sc-cpmentioning

confidence: 99%

“…For a given set of design specifications, the results obtained from the different proposed analytical approaches [7,8,11,12], can be closely co-related in terms of no.…”

Section: Operational Analysis Of Sc-cpmentioning

confidence: 99%

“…As stated before, the operating frequency can be selected independently, given that the on-time of the switches is sufficiently larger than the default RC time constant (R SW • C P ), such that the CP operation under SSC regime is ensured. The work in [12], presents a more generic optimization methodology obtained through a unique representation the SC-CP as a 2-port circuit element. The analysis is specifically applied for power efficiency optimization within the constraints of a given set of design specifications.…”

Section: Simplified Linear Modelmentioning

confidence: 99%

“…In [12], the CP model is more involved, correctly capturing the effect of CP operating frequency on the input power consumption and CP output impedance R out . However, the proposed 2-port CP model, inherently involves a number of assumptions, which cannot be substantiated universally.…”

Section: )mentioning

confidence: 99%

“…In the given design, area utilization is prioritized over power efficiency optimization in order to achieve a compact realization for the fully-integrated charge-pump, which is not constrained with its operation in SSC or FSC regimes. The power efficiency optimization, as covered in a number of previous works [7], [12], [9], mandates the CP operation in SSC and typically results in an area intensive CP implementation. This design aims to explore the feasibility, design and trade-off involved with the CP operation when SSC operation cannot be ascertained.…”

Section: Derivation Of Charge-pump Linear Modelmentioning

confidence: 99%

See 4 more Smart Citations

Design and analysis of a low-noise regulated negative voltage generator system

Khanna¹

View full text Add to dashboard Cite

This thesis presents the design and analysis of a generic, low-noise regulated negative voltage generator, with wide tuning range and moderate driving capability.The highly integrated solution comprises of a multi-phase clock generator, fullyintegrated charge-pump and a regulator block while requiring only one off-chip capacitor that can be shared with supply decoupling capacitors. A novel analysis of the charge-pump module incorporating the effect of non-zero switch resistance and finite on-time of switches, is proposed, and a closed form expression of its output impedance is derived. The resulting frequency dependent charge-pump linear model is included in the regulator setup and utilized for the system level analysis and verification from both small and large signal prospective. This includes ascertaining the stability of the feedback loop, quantifying the charge-pump noise rejection by the regulator module and analysis of the complete settling profile from power-up till steady-state. In addition, the system level performance is further verified through rigorous transient co-simulation of the charge-pump and regulator modules. The overall solution is powered from a single 3.3V DC input and provides an output tuning range from -4.4V to +2.1V for biasing applications. The design also supports a maximum load current of 250µA, 550µA and 800µA for regulated output voltage at -3.0V, -1.5V and 1.5V respectively. The measured steady-state ripple is under 3mV P P while the noise voltage at the charge-pump operating frequency harmonics is below 130µV RM S and the noise-floor is under 5µV RM S . The design is also application verified with a Gallium-Nitride power amplifier, thus further confirming its low-noise performance. Implemented in CMOS 180nm process, the prototype chip occupies an area of 0.55mm 2 .A systematic design methodology, supplemented with an in-depth analysis of CP and regulator modules, ensures robust implementation with reliable performance xi output. An on-chip negative generator can facilitate the integration of alternate technologies with mainstream CMOS, besides allowing the designer to experiment with much wider range of circuits and applications. In this regard, the proposed negative voltage generator with low-noise output, wide-tuning and moderate driving capacity can cater to a wide range of integrated applications over multiple circuit design domains. Moreover, the design and analysis carried out in this work is useful towards the evolution of an on-chip negative voltage source that can be potentially included as a generic IP in future SOCs.

show abstract

Section: Operational Analysis Of Sc-cpmentioning

confidence: 99%

“…For a given set of design specifications, the results obtained from the different proposed analytical approaches [7,8,11,12], can be closely co-related in terms of no.…”

Section: Operational Analysis Of Sc-cpmentioning

confidence: 99%

Section: Simplified Linear Modelmentioning

confidence: 99%

Section: )mentioning

confidence: 99%