A novel hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT)
IntroductionHydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) technology has become the main stream of large-sized active matrix flat-panel displays (FPD) due to the lower process temperature, simpler fabrication process, and better uniformity than the laser-annealed poly-Si TFT [1]- [11]. Moreover, integrated circuits on glass have attracted much attention owing to the advantages such as compactness, mechanical reliability, and the elimination of the external driver ICs which result in overall cost reduction [1]- [9]. Consequently, a-Si:H gate driver circuits are widely used in large-sized displays nowadays. Nevertheless, the a-Si:H TFT suffers from the instabilities including defect-state creation and charge trapping under longterm operation and bias stress, which result in severe threshold voltage (V TH ) shift of the a-Si:H TFT [12]. The life time of the gate driver circuit is also decreased by the V TH shift of the aSi:H TFT. Therefore, reducing V TH shift of the a-Si:H TFT is significant to an a-Si:H gate driver circuit design. Kim et al.[1] proposed an a-Si:H S-R latch gate driver circuit having dcbiased pull-down TFT to stabilize the row line. Despite that the gate -source voltage (V GS ) is reduced to improve the V TH shift of the pull-down TFT, the dc-biased pull-down TFT may still degraded seriously under dc stress and shorten the life time of the circuit. Therefore, Jang et al. [2] proposed an integrated gate driver circuit with ac-driving pull-down TFTs to prevent the row line from floating, and suppress the V TH shift of pulldown TFTs by driving the pull-down TFTs alternatively. Even though the instabilities of the a-Si:H TFT can be diminished by the above methods, the reliability of the gate driver circuit should be further studied and improved for large-sized panels.This work proposed a novel a-Si:H gate driver circuit with 33% duty ratio ac-driving structure to keep the row line from floating, suppress the V TH shift of pull-down TFTs, and reduce the clock signal loading. The V GS of the pull-down TFTs is also lowered to decelerate the rate of the V TH shift. Furthermore, the dimensions of the pull down TFTs are decreased by using driving TFT to charge and discharge the row line. Measurement results showed that the output waveform of the proposed circuit remains almost constant after a 240-h-long 60°C reliability test [5], demonstrating the long-term reliability of the proposed circuit as well as the feasibility of fabricating the proposed circuit for practical use.
Circuit Schematic and OperationAs shown in Fig. 1(a), each stage of the proposed gate driver circuit is composed of nine TFTs and two capacitors. Fig. 1(b