Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

Agbo, Innocent; Taouil, Mottaqiallah; Kraak, Daniël; Hamdioui, Said; Kükner, Halil; Weckx, Pieter; Raghavan, Praveen; Catthoor, Francky

doi:10.1109/tvlsi.2016.2643618

Cited by 34 publications

(17 citation statements)

References 33 publications

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“…In both cases, this triggers read/write operations to/from the memory. These memory operations determine the workload of the memory and, thus, they strongly impact its aging [16], [17]. The idea proposed in this paper is to optimize the memory instructions issued by applications in order to mitigate the memory's aging.…”

Section: Proposed Methodologymentioning

confidence: 99%

Software-Based Mitigation for Memory Address Decoder Aging

Kraak

Gürsoy

Agbo

et al. 2019

2019 IEEE Latin American Test Symposium (LATS)

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Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary to achieve the desired reliability. However, these increased margins lead to a reduced performance and lower yield. Alternatively, mitigation schemes can be deployed to reduce the aging. This paper proposes a software-based method to mitigate the aging of the memory's address decoder logic due to Bias Temperature Instability. The method is based on periodically applying a rejuvenation application on top of a user application. The goal of the rejuvenation application is to recover aged transistors of the critical paths of the address decoder. The experimental results show that the proposed method significantly reduces aging in cases when applications consist of memory access patterns that result in an unbalanced stress in the address decoder logic. In particular, it reduces the degradation of the address decoder's setup delay by up to 43% with an execution overhead of only 1%.

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Section: Proposed Methodologymentioning

confidence: 99%

Software-Based Mitigation for Memory Address Decoder Aging

Kraak

Gürsoy

Agbo

et al. 2019

2019 IEEE Latin American Test Symposium (LATS)

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“…Since most of the transistors have enough time to recover (releasing trapped charges) from the stress accumulated during the active periods, only the pseudopermanent part of the BTI aging is conserved between execution periods. Nevertheless, this performance degradation must be taken into account during the design of the biomedical device, particularly because the impact of BTI is expected to increase with future reductions in transistor size [3], [32]. Alternatively, the tighter determination of safe operating conditions of our framework with respect to STA can enable the selection of lower supply voltages for the same latency target, with the corresponding savings in energy consumption.…”

Section: Bti Impact On Maximum Frequencymentioning

confidence: 99%

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

Duch

Peón-Quirós

Weckx

et al. 2020

IEEE Trans. VLSI Syst.

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Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, bias temperature instability (BTI) is a degradation effect that changes the threshold voltage of transistors. Its effect is more prevalent as the scaling of transistor dimensions progresses. In this work, we present a method to enable defect-centric long-term modeling of BTI degradation that takes into account the effects of concrete workloads at the processor data path level. Based on this study, we propose a novel design flow to link the impact of BTI degradation at the transistor (∆V th), processor data path (e.g., maximum frequency) and application-functionality levels. This flow may be used to improve system correctness over the entire device lifetime, avoiding unsafe working points, or to achieve a graceful degradation of system characteristics. Our design flow is applicable to all types of digital circuits, including high-performance processors. However, in this specific work we focus on the domain of biosignal processing applications for wireless body sensor networks (WBSNs), whose pseudo-periodic nature interacts with the partially recoverable nature of BTI. Our results in this domain show, for a 32 nm implementation, a variation of up to 54.6 mV in the threshold voltage of the circuit transistors after one year of continuous operation, with an impact of 8.4 % in the maximum safe operating frequency. Such effects are expected to strongly worsen for longer lifetimes and more scaled technology nodes.

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“…We investigated the impact of BTI on the standard latch-type SA design as a result of its superior performance. In addition, we analyzed the impact on process, voltage, and temperature (PVT) variations in combination with BTI for different workloads and technology nodes [179].…”

Section: Investigation Of Aging Impact and Mitigation On Memory Read-mentioning

confidence: 99%

Reliability Modeling and Mitigation for Embedded Memories

Agbo

Taouil

Hamdioui

2019

2019 IEEE International Test Conference (ITC)

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Complementary Metallic Oxide Semiconductor (CMOS) technology scaling enhances the performance, transistor density, functionality, and reduces cost and power consumption. However, scaling causes significant reliability challenges both from a manufacturing and operational point of view. Obtaining reliable memories require accurate understanding of the impact of aging (such as Bias temperature instability (BTI)) on individual memory components and how they interact with each other. In this dissertation, two types of challenges are addressed, which are related to BTI aging and partially to mitigation schemes: one related to the aging of sense amplifier and another one to the aging of read path and write path. Analysis of aging impact on different memory sense amplifiers-The analysis of BTI impact on various memory sense amplifier (SA) designs was performed, while taking into account two BTI models (i.e., Atomistic and RD model), different technology nodes (i.e., 90, 65, 45, 32, 22, and 16 nm), and different workloads. First, the analysis and comparison of RD and Atomistic models impact on the SA were performed. The results show that the atomistic trap-based BTI model is more accurate than the RD model. Second, the investigation of BTI impact on the drain-input latch type SA for various technology nodes and supply voltages was performed. The result shows that as technology scales down, the impact of BTI on sensing delay increases, while the sensing voltage decreases, causing less robust and reliable memory sense amplifier. The result also shows that increase in supply voltage compensates the BTI degradation. Third, an accurate technique was proposed and characterized for the integral impact of BTI and voltage temperature variation on the memory standard latch type SA for various technology nodes and workloads. The results show that the degradation is strongly dependent on workload and temperature. Fourth, in addition to the latter, the impact of process variation at timezero was incorporated and analyzed. The results show that the SA sensing delay degradation is more significant at lower nodes and could lead to read failures at lower power supply. This reveals that there must be a tradeoff between performance and reliability. Fifth, an accurate methodology was proposed to quantify the impact of variability on the memory SA offset-voltage for both time-zero and time-dependent variability. The results show that the impact on the offset voltage specification is significant for aging time-dependent variability. Sixth, on top of the latter, the sensitivity of the SA and its failure rate were analyzed for five process corners (i.e., Nominal, Fast-Fast, Fast-Slow, Slow-Fast, and Slow-Slow). The results show that balanced workloads result in a significant low offset voltage specification. Finally, the impact of aging was analyzed and compared, while considering different supply voltages, temperatures, and SA designs. The results show that the High Performance SA degrades faster than other SA types, irrespective of the workloa...

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Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier

Cited by 34 publications

References 33 publications

Software-Based Mitigation for Memory Address Decoder Aging

Software-Based Mitigation for Memory Address Decoder Aging

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

Reliability Modeling and Mitigation for Embedded Memories

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