Instruction-level parallel processing: History, overview, and perspective

Rau, B. Ramakrishna; Fisher, Joseph A.

doi:10.1007/bf01205181

Cited by 232 publications

(61 citation statements)

References 132 publications

(13 reference statements)

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“…The operators of the loop executed before the loop body after the transformation (f) form the loop prolog, the operators executed after the body (g) are the loop epilog, and the interval at which iterations are started is the initiation interval (II). The goal of pipelining is to achieve the minimum possible II, which is hardware resource or data dependence constrained [16]. Chapter 4…”

Section: Pipeliningmentioning

confidence: 99%

Efficient pipelining of nested loops: unroll-and-squash

Petkov

Harr²,

Amarasinghe³

2002

Proceedings 16th International Parallel and Distributed Processing Symposium

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The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology to map abstract designs into silicon. Many applications operating on large streaming data usually require a custom VLSI because of high performance or low power restrictions. Since the data processing is typically described by loop constructs in a high-level language, loops are the most critical portions of the hardware description and special techniques are developed to optimally synthesize them. In this thesis, we introduce a new method for mapping nested loops into hardware and pipelining them efficiently. The technique achieves fine-grain parallelism even on strong intra-and inter-iteration datadependent inner loops and, by economically sharing resources, improves performance at the expense of a small amount of additional area. We implemented the transformation within the Nimble Compiler environment and evaluated its performance on several signal-processing benchmarks. The method achieves up to 2x increase in the area efficiency compared to the best known optimization techniques.

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Section: Pipeliningmentioning

confidence: 99%

Efficient pipelining of nested loops: unroll-and-squash

Petkov

Harr²,

Amarasinghe³

2002

Proceedings 16th International Parallel and Distributed Processing Symposium

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“…The early work on parallel instruction scheduling for processors was carried out in the context of microcode compaction [9][10][11]. The pre-scheduling steps such as the construction of dependence graphs are also examined in [12].…”

Section: Related Workmentioning

confidence: 99%

Efficient backtracking instruction schedulers

Abraham

Meleis

Baev

Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)

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Current schedulers for acyclic regions schedule operations in dependence order and never revisit or undo a scheduling decision on any operation. In contrast, backtracking schedulers may unschedule already scheduled operations, in order to make space for the operation currently being scheduled. Backtracking schedulers have the potential for generating better schedules, e.g. more effectively filling branch delay slots, but are more compile-time intensive and therefore, not considered practical for production use.In this report, we first describe conventional cycle and list schedulers followed by two novel backtracking schedulers. The full-backtracking OperBT scheduler enables backtracking for all operations and unschedules already scheduled operations to make space for the current operation, if, among other situations, there is no available slot that satisfies dependence constraints. This scheduler is effective in generating high quality schedules that for instance, successfully fill branch delay slots but likely backtracks too often. The selective backtracking ListBT scheduler enables backtracking only when scheduling certain types of operations, for which backtracking is likely to be advantageous, e.g. branches. When not scheduling these operations (or operations that were displaced through backtracking), the scheduler reverts to efficient scheduling in dependence order. The ListBT scheduler backtracks less often than the OperBT scheduler. Both schedulers successfully fill a large fraction of the branch delay slots and improve performance of the scheduled code significantly.

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“…Software pipelining has been found to be an efficient compilation technique that results in significant performance improvement at runtime [9,10,15,16]. Modeling of resource constraints (or structural hazards) in software pipelining is becoming increasingly complex in modern processor architectures.…”

Section: Background and Motivationmentioning

confidence: 99%

“…Conventional approaches to model resource constraints uses a simple reservation table (see Figure 1(a)) [13,10,9,15,16]. The state diagram approach is a systematic and effective way to represent the resource usages and conflicts when multiple operations of a loop are scheduled [6].…”

Section: Introductionmentioning

confidence: 99%

“…Recent studies on modulo scheduling, an instruction scheduling method for loops [9,10,15,16,3], in a production compiler has reported significant improvement (up to 35%) in the overall runtime for a suite of SPEC floating point benchmark programs [17]. On the other hand, rapid advances in VLSI technology and computer architecture present an important challenge for compiler designers: a modulo scheduler must be able to handle machine resource constraints much more complex than before and may need to search for an increasingly larger number of schedules before a desirable one is chosen.…”

Section: Introductionmentioning

confidence: 99%

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Efficient State-Diagram Construction Methods for Software Pipelining

Zhang

Govindarajan

Ryan

et al. 1999

Lecture Notes in Computer Science

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Abstract.State diagram based approach has been proposed as an effective way to model resource constraints in traditional instruction scheduling and software pipelining methods. However, the constructed state diagram for software pipelining method (i) is very large and (ii) contains significant amount of replicated, and hence redundant, information on legal latency sequences. As a result, the construction of state diagrams can take very large computation time. In this paper, we propose two methods for the efficient construction of state diagrams. In the first method, we relate the construction of state diagram to a well-known problem in graph theory, namely the enumeration of maximal independent sets of a graph. This facilitates the use of an existing algorithm as a direct method for constructing distinct latency sequences. The second method is a heuristic approach which exploits the structure of state diagram construction to eliminate redundancy at the earliest opportunity in an aggressive fashion. The heuristic method uses a surprisingly simple check which is formally shown to completely eliminate redundancy in the state diagram. From our experimental results on two real architectures, both of the two methods show a great reduction in state diagram construction time.

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Instruction-level parallel processing: History, overview, and perspective

Cited by 232 publications

References 132 publications

Efficient pipelining of nested loops: unroll-and-squash

Efficient pipelining of nested loops: unroll-and-squash

Efficient backtracking instruction schedulers

Efficient State-Diagram Construction Methods for Software Pipelining

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