Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors

Abstract

We investigate instruction distribution methods for quadcluster, dynamically-scheduled superscalar processors. We study a variety of methods with different cost, performance and complexity characteristics. We investigate both non-adaptive and adaptive methods and their sensitivity both to inter-cluster communication latencies and pipeline depth. Furthermore, we develop a set of models that allow us to identify how well each method attacks issue-bandwidth and inter-cluster communication restrictions. We find that a relatively simple method that changes clusters every other three instructions offers only a 17% performance slowdown compared to a nonclustered configuration operating at the same frequency. Moreover, we show that by utilizing adaptive methods it is possible to further reduce this gap down to about 14%. Furthermore, performance appears to be more sensitive to inter-cluster communication latencies rather than to pipeline depth. The best performing method offers a slowdown of about 24% when inter-cluster communication latency is two cycle. This gap is only 20% when two additional stages are introduced in the front-end pipeline.

Partitioning Multi-Threaded Processors with a Large Number of Threads

“…The only drawback of such an architecture is the intercluster communication cost. Various groups [2,3,4,6,9,10] have studied cluster assignment mechanisms for one thread to reduce the overhead of inter-cluster communication. We extend their ideas to a clustered architecture with multiple threads.…”

Clustered multithreaded architectures -pursuing both IPC and cycle time

“…Baniasadi and Moshovos evaluate various queue clustering schemes for a single threaded processor [4]. This work focuses on queue assignment schemes when the instruction queue is split into four queues.…”

“…Various queue assignment schemes have been proposed which assign instructions to queues, utilizing instruction specific information. For example, the branch-cut scheme [4] assigns instructions to the same instruction queue until a branch is encountered, at which point a new queue is chosen. Each of these schemes is extended and modified to work within a multithreaded architecture.…”

“…How permanent is the queue assignment? For the first option, we consider a high-performing subset of previously proposed instruction steering mechanisms: (1) mod4 switches queues every 4 instructions [4].…”

“…(2) branch-cut switches queues after each branch [4]. (3) seek dependencies sends instructions to the queue which contains the younger parent of the instruction under consideration, unless all operands are already available [4].…”