Influences of two-step growth and off-angle Ge substrate on crystalline quality of GaAs buffer layers grown by MOVPE

Wanarattikan, Pornsiri; Sanorpim, Sakuntam; Denchitcharoen, Somyod; Uesugi, Kenjiro; Kuboya, Shigeyuki; Onabe, Kentaro

doi:10.1016/j.jcrysgro.2014.11.027

Cited by 10 publications

(14 citation statements)

References 29 publications

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“…Then, the influence of different angles of the Si substrate on the inhibition of APB is also discussed. Wanarattikan et al [ 87 ] grew GaAs layers with two-step growth on miscut Ge (001) substrates mis-oriented by big angles between 4° and 6° towards [110] direction. They found that APBs were limited at the 20–30 nm GaAs/Ge interface, while APBs-free 480 nm GaAs regions can be significantly obtained on the 6° miscut Ge (001) substrates with the RMS of 0.9 nm.…”

Section: Latest Approach Of Heteroepitaxy Of Si-based Iii-v Group Mat...mentioning

confidence: 99%

“…Multi-step epitaxial growth such as three-step or four-step, which insert intermediate temperature growth, helps to prevent nuclear island forming in a metastable state from being reconstructed or damaged at high temperature. Wanarattikan et al [ 87 ] studied the effect of the process of two-step growth and one-step growth on GaAs buffer layers using miscut Ge substrates. They designed the two-step growth with: low temperature growth at 470 °C and high temperature growth at 580 °C.…”

Section: Latest Approach Of Heteroepitaxy Of Si-based Iii-v Group Mat...mentioning

confidence: 99%

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Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

Wang

et al. 2022

Nanomaterials

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Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized

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Section: Latest Approach Of Heteroepitaxy Of Si-based Iii-v Group Mat...mentioning

confidence: 99%

Section: Latest Approach Of Heteroepitaxy Of Si-based Iii-v Group Mat...mentioning

confidence: 99%

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

Wang

et al. 2022

Nanomaterials

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“…To suppress the dislocation density, some mature epitaxial technologies e.g., dislocation filter layers, buffer layer, low temperature/high temperature (LT/HT) technology, thermal cycling annealing, CMP after epitaxy, cut-off substrates, and necessary pre-treatment, are applied. It is worthy of note that the surface of cut-off substrate, of which oriented to (001) direction is 4°, 6°, etc., can effectively annihilate the APDs, as shown in Figure 45 c. Another way to improve the epi-layer quality is to grow stacks of Ga-Ga or As-As bonds from two odd-atom steps converge and annihilate before it penetrates the whole GaAs epi-layer [ 315 , 316 , 317 ].…”

Section: Iii-v Materialsmentioning

confidence: 99%

“…It is worthy of note that the surface of cut-off substrate, of which oriented to (001) direction is 4 • , 6 • , etc., can effectively annihilate the APDs, as shown in Figure 45c. Another way to improve the epi-layer quality is to grow stacks of Ga-Ga or As-As bonds from two odd-atom steps converge and annihilate before it penetrates the whole GaAs epi-layer [315][316][317].…”

Section: Global Epitaxymentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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“…Although the lower temperature regime reduces the diffusion of Ge into the GaAs layer [14], the higher temperature regime reduces the carbon contamination in the GaAs layer [21]. Furthermore, it is frequent to observe diamond-shape APB-related defects at the GaAs/Ge interface with the low-temperature growth regime [3,15,22]. In addition, using the higher temperature regime, devices grown on Ge substrates such as lasers and solar cells have shown comparable and even better performances than on GaAs substrate [18,21].…”

Section: Introductionmentioning

confidence: 99%