Influence of Transfer Gate Design and Bias on the Radiation Hardness of Pinned Photodiode CMOS Image Sensors

Goiffon, Vincent; Estribeau, Magali; Cervantes, Paola; Molina, Romain; Gaillardin, M.; Magnan, Pierre

doi:10.1109/tns.2014.2360773

Cited by 38 publications

(27 citation statements)

References 31 publications

(86 reference statements)

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“…In other words, this measurement shows that there is no bulk RTS centers in the studied device. When the transfer gate voltage is higher than 0.7V, the potential below the transfer gate is higher than the potential in the PPD, so that the generated dark charges go directly to the sense node instead of being stored in the photodiode (as detailed in [17]). Hence, the RTS centers have not disappeared but their contribution is no more visible.…”

Section: B Influence Of Design Parametersmentioning

confidence: 99%

Total Ionizing Dose Radiation-Induced Dark Current Random Telegraph Signal in Pinned Photodiode CMOS Image Sensors

Durnez

Goiffon

Virmontois

et al. 2018

IEEE Trans. Nucl. Sci.

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In this work, several studies on Total Ionizing Dose effects on Pinned Photodiode CMOS images sensors are presented. More precisely, the evolution of a parasitic signal called Random Telegraph Signal is analysed through several photodiode designs. It is shown that the population of pixels exhibiting this fluctuation depends on the design variants. This population also increases in a different way with the dose: the effects are not same considering a low or high X-rays irradiation. Moreover, a statistical analysis is realized in order to better caracterize the defects responsible for RTS. It turns out that electric field enhancement signature can appear in some specific cases.

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Section: B Influence Of Design Parametersmentioning

confidence: 99%

Total Ionizing Dose Radiation-Induced Dark Current Random Telegraph Signal in Pinned Photodiode CMOS Image Sensors

Durnez

Goiffon

Virmontois

et al. 2018

IEEE Trans. Nucl. Sci.

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“…Understanding the effect of temperature can be of great importance as it can highlight the variation of one specific parameter (such as the dark current, the pinning voltage or the TG threshold voltage and leakage current) following geometrical variations or radiation campaigns [19]. This paper also discussed the dynamic behavior of the FWC in nonsteady-state light conditions.…”

Section: Discussionmentioning

confidence: 99%

Temperature Dependence and Dynamic Behavior of Full Well Capacity in Pinned Photodiode CMOS Image Sensors

Pelamatti

Belloir

Messien

et al. 2015

IEEE Trans. Electron Devices

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This paper presents an analytical model of the full well capacity (FWC) in pinned photodiode (PPD) CMOS image sensors. By introducing the temperature dependence of the PPD pinning voltage, the existing model is extended (with respect to previous works) to consider the effect of temperature on the FWC. It is shown, with the support of experimental data, that whereas in dark conditions the FWC increases with temperature, a decrease is observed if FWC measurements are performed under illumination. This paper also shows that after a light pulse, the charge stored in the PPD drops as the PPD tends toward equilibrium. On the basis of these observations, an analytical model of the dynamic behavior of the FWC in noncontinuous illumination conditions is proposed. The model is able to reproduce experimental data over six orders of magnitude of time. Both the static and dynamic models can be useful tools to correctly interpret FWC changes following design variations and to accurately define the operating conditions during device characterizations.Index Terms-Active pixel sensor (APS), analytical modeling, capacitance, CMOS image sensor (CIS), dynamic behavior, full well capacity (FWC), modeling, pinned photodiode (PPD), pinning voltage, temperature.

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“…In the first instance (a), the TG is off, being held at 0 V. In the second instance (b), the TG is 'on' (and held in this state for time: tTRA) and is pulsed at 'VTRA high' voltage (suggested to be 3.15 V to 3.45 V, with typical value being 3.3 V). In both instances, the FD is held at a reference voltage (VREFR), which is recommended by Teledyne e2v to be between 2.8 V and 3.0 V. The pinning voltage of the device characterises the PPD potential and can typically be estimated using the method shown in [8]. These tests are typically carried out for characterisation of every device at the Open University.…”

Section: Potential Profile Of the Cis115mentioning

confidence: 99%

Image lag optimisation in a 4T CMOS image sensor for the JANUS camera on ESA's JUICE mission to Jupiter (Conference Presentation)

Lofthouse-Smith

Soman

Allanwood

et al. 2018

High Energy, Optical, and Infrared Detectors for Astronomy VIII

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The CIS115, the imager selected for the JANUS camera on ESA's JUICE mission to Jupiter, is a Four Transistor CMOS Image Sensor (CIS) fabricated in a 0.18 µm process. 4T CIS (like the CIS115) transfer photo generated charge collected in the pinned photodiode to the sense node through the Transfer Gate. These regions are held at different potentials and charge is transferred from the potential well under the pinned photodiode to the potential well under the sense node through a voltage pulse applied to the transfer gate. Incomplete transfer of this charge can result in image lag, where signal in previous frames can manifest itself in subsequent frames, often appearing as ghosted images in successive readouts, seriously affecting image quality in scientific instruments, which must be minimised. This is important in the JANUS camera, where image quality is essential to help JUICE meet its scientific objectives. Image lag investigation in this paper compare results pre and post Total Ionizing Dose and documents a decrease in image lag following Total Ionizing dose below device full well capacity, scaled with dose. This paper also presents two techniques to minimise image lag within the CIS115. An analysis of the optimal voltage for the transfer gate voltage is detailed where optimisation of this TG "ON" voltage has shown to minimise image lag in both an engineering model, gamma and proton irradiated devices. Secondly, a new readout method of the CIS115 is described, where following standard image integration, the PPD is biased to the reset voltage level (VRESET) through the transfer gate to empty charge on the PPD and has shown to reduce image lag in the CIS115

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Influence of Transfer Gate Design and Bias on the Radiation Hardness of Pinned Photodiode CMOS Image Sensors

Cited by 38 publications

References 31 publications

Total Ionizing Dose Radiation-Induced Dark Current Random Telegraph Signal in Pinned Photodiode CMOS Image Sensors

Total Ionizing Dose Radiation-Induced Dark Current Random Telegraph Signal in Pinned Photodiode CMOS Image Sensors

Temperature Dependence and Dynamic Behavior of Full Well Capacity in Pinned Photodiode CMOS Image Sensors

Image lag optimisation in a 4T CMOS image sensor for the JANUS camera on ESA's JUICE mission to Jupiter (Conference Presentation)

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