Influence of gate internal impedance on losses in a power MOS transistor switching at a high frequency in the ZVS mode

Abstract

In order to use a power MOS transistor in the ZVS mode at high switching frequencies, the output capacitance has to be maximal and the input capacitance minimal. These characteristics available in the datasheets have to be completed if necessary tu choose the ideal transistor for application with minimal losses, and additional characterisations have to be realised in order to specify or complete the datasheets. In particular, it is necessary to be sure that all the cells of the MOS transistor can be opened in a short time before the voltage rise time at turn-off, in order to reduce as low as possible turn-off losses. The paper points out that the gate to source impedance characterises the ability of the device to turn-off very quickly and is useful to choose a MOS transistor having minimal losses in very high switching frequency ZVS applications.

Overcoming switching limits in silicon power MOSFETs with silicon‐based solutions

“…Another reason is the buried polysilicon forming the plate electrode which, unlike the gate polysilicon, cannot be salicided. As a result, propagation delay across the layout is susceptible to occur due to an internal R sh at the plate [15, 16].…”