Influence of Dry Recess Process on Enhancement-Mode GaN Metal–Oxide–Semiconductor Field-Effect Transistors

Abstract

To gain a flat recess profile with uniform etching depth, dry recess experiment with different inductively coupled plasma (ICP) etching conditions was done on an AlGaN/GaN heterostructure. Trenching effect at the bottom near the sidewall was observed when positive photoresist was utilized and the ICP power was low. The recess profile was improved by adopting SiO2 as the etching mask and increasing the ICP power. GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with different gate recess conditions were fabricated and characterized. The maximum field-effect mobility of 152.8 cm-2 V-1 s-1 and the minimum interface state density of 1.39×1011 cm-2 eV-1 were obtained from the optimized gate recess condition with ICP power of 100 W, bias power of 20 W and etching mask of SiO2.

Reduction of leakage current by O2 plasma treatment for device isolation of AlGaN/GaN heterojunction field-effect transistors

“…This broad luminescence band could be attributed to transition from a shallow donor to a deep acceptor [7,8]. The shallow donor of the etched u-GaN may be the etching damage of the nitrogen vacancy V N according to our previous work [9,10], whereas the deep acceptor may be the native defect of the gallium vacancy V Ga [11][12][13]. The near band-edge luminescence intensity of all the samples was weaker than the YL intensity, which could be primarily attributed to the non-radiative centers at low doping concentrations in the u-GaN layer [14][15][16].…”

Gate-first GaN MOSFET based on dry-etching-assisted non-annealing ohmic process

“…Owing to the dry etching damage in the gate recess process, the threshold voltages of both devices are about −3 V. The nitrogen vacancy (V N ) caused by the dry etching damage would form an n-type layer on the etched surface and should be responsible for the negative threshold voltage. 17,18) The gate-first device shows a maximum field-effect mobility of 163.8 cm 2 V −1 s −1 , which is relatively higher than that of the ohmic-first device on the same n + -GaN=SI-GaN wafer, and also higher than that of the ohmic-first device on the AlGaN=SI-GaN wafer in our previous experiments. 8,19,20) In summary, a non-annealing ohmic process was investigated and the results show that aside from the higher etching power, a higher substrate doping density is also necessary to form a non-annealing ohmic contact.…”

Gate structure dependent normally-off AlGaN/GaN heterostructure field-effect transistors with p-GaN cap layer

“…Therefore, the reverse drain leakage current is from the gate leakage, which is likely from the sidewall damage. Generally, the p-GaN cap layer is removed by inductively coupled plasma (ICP) etching using photoresist as the mask, which will introduce lattice damage in the sidewall of p-GaN [20]. Those damages will provide a leakage path across the sidewall surface of the p-GaN and i-GaN layers [21,22].…”