Influence of Device Performance of Sub-15 nm high K dielectric-based MOSFETs over Conventional Si-based MOSFETs.

Abstract

A channel-engineered single insulator gate metal oxide field effect transistor (MOSFET) for low-power digital circuitry has been proposed in this study. This study examines the effects of several dielectric insulators used as gate materials, silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium dioxide (HfO2), and zirconium dioxide (ZrO2). The device's performance parameters are enhanced by utilizing different dielectrics in MOSFETs as a gate dielectric since the leakage current is significantly decreased. Following the validation of simulation findings using MOSFET reference data, the structure is evaluated by 15nm and 20nm node technology. In particular 15 nm scale, MOSFET exhibits reduced IOFF, higher ION/IOFF ratio, enhanced Drain Induced Barrier Lowering (DIBL), and Sub-threshold Slope (SS). For proposed MOSFETs, the simulated values of ION, IOFF, ION/IOFF, SS, DIBL, TGF, output conductance (gd), intrinsic gain (Av), and early voltage (VEA) shows improvements which are helpful in digital logic applications.