Influence of BEOL process on poly-Si grain boundary traps passivation in 3D NAND flash memory

Zhao, Yuexin; Li, Jun; Hua, Ziqun; Jin, Lei; Huo, Zongliang

doi:10.1016/j.sse.2019.03.026

Cited by 14 publications

(7 citation statements)

References 13 publications

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“…However, these degradation problems can be optimized through appropriate post-processing is used to fill in the defects that are not completely passivated and the pre-existing defects in the active layer of the device. 32 This result will help the development of next-generation high-resolution display devices.…”

Section: Discussionmentioning

confidence: 95%

Investigation of degradation mechanisms in small scaled amorphous-indium-gallium-zinc-oxide thin-film-transistors

Xin

Cui

Kim

et al. 2021

ECS J. Solid State Sci. Technol.

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We measured the stability of small-sized trench devices with different specifications under negative bias. The degradation behavior of the electrical characteristics of the device caused by the channel size was analyzed. It was found that the passivation caused by the increase of the channel width was not completely generated by charge trapping in the passivation layer and the interface between the passivation layer and the active layer. The parasitic effect related to the channel length and the drain-induced barrier lowering effect together affect the electrical stability of the device. This shows that with the development of small-sized TFT devices, the influence of size on the device begins to appear. As such the size factor must be considered when designing the device. For the instability caused by these devices themselves, post-processing can be used to improve the stability.

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Section: Discussionmentioning

confidence: 95%

Investigation of degradation mechanisms in small scaled amorphous-indium-gallium-zinc-oxide thin-film-transistors

Xin

Cui

Kim

et al. 2021

ECS J. Solid State Sci. Technol.

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“…An aggressive device scaling with higher level of complex integration is a major trend for device development leading to technical advances such as three-dimensional (3D) vertical stacked structures. As an example, polycrystalline silicon (poly-Si) channel has been widely used for vertical-NAND flash memory and back-end-of-line (BEOL) transistors. , However, poly-Si channels suffer from critical limitations for further device scaling due to the degradation in carrier mobility and the poor uniformity in device characteristics caused by grain-boundary effects. − Furthermore, the 3D integration and cell size reduction, which correspond to the ultimate path toward higher-density DRAM, is now facing such problems as an implementation of highly scaled storage capacitor. Alternatively, amorphous oxide semiconductors (AOS) have been considered as one of the most promising channel materials for the BEOL transistors and monolithic 3D integration in future logic and memory applications such as capacitor-less DRAM due to their large-area uniformity, competitive carrier mobility, and ultralow leakage current components. , …”

Section: Introductionmentioning

confidence: 99%

Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with Subμm Channel Lengths

Bae

Yang

Kim

et al. 2022

ACS Appl. Mater. Interfaces

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Roles of oxygen interstitial defects located in the In–Ga–Zn-O (IGZO) thin films prepared by atomic layer deposition were investigated with controlling the cationic compositions and gate-stack process conditions. It was found from the spectroscopic ellipsometry analysis that the excess oxygens increased with increasing the In contents within the IGZO channels. While the device using the IGZO channel with an In/Ga ratio of 0.2 did not show marked differences with the variations in the oxidant types during the gate-stack formation, the device characteristics were severely deteriorated with increasing the In/Ga ratio to 1.4, when the Al2O3 gate insulator (GI) was prepared with the H2O oxidants (H2O–Al2O3) due to a higher amount of excess oxygen in the channel. Additionally, during the deposition process of the Al-doped ZnO (AZO) gate electrode (GE) replacing from the indium–tin oxide (ITO) GE, the thermal annealing effect at 180 °C facilitated the passivation of oxygen vacancy and the strengthening of metal–oxygen bonding, which could stabilize the TFT operations. From these results, the gate-stack structure employing O3-processed Al2O3 GI (O3–Al2O3) and AZO GE (OA) was suggested to be most suitable for the device using IGZO channel with a higher In content. On the other hand, the device employing H2O–Al2O3 GI and AZO GE exhibited larger negative shifts of threshold voltage (V TH) under positive-bias-temperature stress (PBTS) condition than the device employing O3– Al2O3 GI and ITO GE due to larger hydrogen contents within the gate stacks. Anomalous negative shifts of V TH were accelerated with increasing the In contents of the IGZO channel. When the channel length of the fabricated device were scaled down to submicrometer regime, the OA gate stacks successfully alleviated the short-channel effects.

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“…The GBs typically act as trap sites to capture charge carriers, and these trapped charges generate potential barriers in the GBs. The trap/detrap phenomena of the charge carriers and the barrier formations impede carrier transport in the poly-Si channel layer, resulting in degradation of the device performance and variability. − From the viewpoint of good device scaling to achieve both device miniaturization and performance improvement, a new channel material should be considered, and oxide semiconductors with multiple elements such as In–Ga–Zn–O (IGZO), , In–Ga–Sn–O (IGTO), and In–Zn–Sn–O (IZTO) , could be promising candidates. Sputtering has been a conventional deposition method of oxide semiconductor thin films, but now atomic-layer deposition (ALD) is regarded as an advanced technique in terms of no aging of the sputtering target, accurate control of cationic compositions, good quality of the deposited films, and film conformality for future semiconductor devices with 3D structures …”

Section: Introductionmentioning

confidence: 99%

Device Characterization of Nanoscale Vertical-Channel Transistors Implemented with a Mesa-Shaped SiO₂ Spacer and an In–Ga–Zn–O Active Channel

Ryoo

Ahn

Seong³

et al. 2021

ACS Appl. Electron. Mater.

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A nanoscale vertical-channel thin film transistor (V-TFT) with a channel length shorter than 160 nm was fabricated and characterized, in which In−Ga−Zn−O (IGZO) and SiO 2 thin films were prepared by atomic layer deposition and plasmaenhanced chemical-vapor deposition as active and spacer layers, respectively. The prototype device showed sound transistor operation with an on/off ratio of 8.8 × 10 3 and robust stabilities without any shift in transfer curves under positive/negative bias stresses at 1 MV/cm for 10 4 s. It was also noteworthy that there was no anomalous increase in off-state current during the positive bias stress test, which is suggested to originate from a high-quality interface between the SiO 2 spacer and IGZO active layers on the back-channel region. Alternatively, high off-state current levels were found to result from the formation of conduction paths generated by carbon-related residues on the vertical back-channel region through the surface time-of-flight secondary ion mass spectrometer analysis. Improvements in device performance and analysis of operation failures will provide insight into the implementation of nanoscale oxide V-TFTs.

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Influence of BEOL process on poly-Si grain boundary traps passivation in 3D NAND flash memory

Cited by 14 publications

References 13 publications

Investigation of degradation mechanisms in small scaled amorphous-indium-gallium-zinc-oxide thin-film-transistors

Investigation of degradation mechanisms in small scaled amorphous-indium-gallium-zinc-oxide thin-film-transistors

Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with Subμm Channel Lengths

Device Characterization of Nanoscale Vertical-Channel Transistors Implemented with a Mesa-Shaped SiO₂ Spacer and an In–Ga–Zn–O Active Channel

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Influence of BEOL process on poly-Si grain boundary traps passivation in 3D NAND flash memory

Cited by 14 publications

References 13 publications

Investigation of degradation mechanisms in small scaled amorphous-indium-gallium-zinc-oxide thin-film-transistors

Investigation of degradation mechanisms in small scaled amorphous-indium-gallium-zinc-oxide thin-film-transistors

Roles of Oxygen Interstitial Defects in Atomic-Layer Deposited InGaZnO Thin Films with Controlling the Cationic Compositions and Gate-Stack Processes for the Devices with Subμm Channel Lengths

Device Characterization of Nanoscale Vertical-Channel Transistors Implemented with a Mesa-Shaped SiO2 Spacer and an In–Ga–Zn–O Active Channel

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Product

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Device Characterization of Nanoscale Vertical-Channel Transistors Implemented with a Mesa-Shaped SiO₂ Spacer and an In–Ga–Zn–O Active Channel