iNFAnt

Cascarano, N.; Rolando, P.; Risso, Fulvio; Sisto, Riccardo

doi:10.1145/1880153.1880157

Cited by 78 publications

(19 citation statements)

References 7 publications

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“…Realistic scenario: This scenario quantifies the performance gains of GPU acceleration for packet classification in a real setting (Sec- 3 . Figure 3 plots the cumulative distribution function (CDF) of the number of rules per class for the ACL, IPF, and IPC rule sets, respectively.…”

Section: Experimental Methodologymentioning

confidence: 99%

“…Graphics processing units (GPUs) have been applied to several computation-intensive applications, such as IP lookup [10,14,26] and pattern matching [3,13,25]. More recently, GPUs have also been adopted to improve the performance of general packet classifiers [10,11].…”

Section: Related Workmentioning

confidence: 99%

“…Due to their high parallelism, graphics processing units (GPUs) have been recently proposed to accelerate several software functions, such as IP lookup [10,14,26], pattern matching [3,13,25], and packet classification [10,11]. However, the performance evaluation of recent GPU-based packet classifiers [10,11] shows that they still cannot sustain high packet I/O rates as the size and dimension of forwarding tables grow, e.g., the case of SDN.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Multi-Layer Packet Classification with Graphics Processing Units

Varvello

Laufer²,

Zhang

et al. 2014

Proceedings of the 10th ACM International on Conference on Emerging Networking Experiments and Technologies

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The rapid growth of server virtualization has ignited a wide adoption of software-based virtual switches, with significant interest in speeding up their performance. In a similar trend, software-defined networking (SDN), with its strong reliance on rule-based flow classification, has also created renewed interest in multi-dimensional packet classification. However, despite these recent advances, the performance of current software-based packet classifiers is still limited, mostly by the low parallelism of general-purpose CPUs. In this paper, we explore how to accelerate packet classification using the high parallelism and latency-hiding capabilities of graphic processing units (GPUs). We implement GPU-accelerated versions for both linear and tuple search, currently deployed in virtual switches, and also introduce a novel algorithm called Bloom search. These algorithms are integrated with high-speed packet I/O to build GSwitch, a GPU-accelerated software switch. Our experimental evaluation shows that GSwitch is at least 7x faster than an equally-priced CPU classifier and is able to reach 10 Gbps with minimum-sized packets and a rule set containing 128K OpenFlow entries with 512 different wildcard patterns.

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Section: Experimental Methodologymentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Multi-Layer Packet Classification with Graphics Processing Units

Varvello

Laufer²,

Zhang

et al. 2014

Proceedings of the 10th ACM International on Conference on Emerging Networking Experiments and Technologies

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“…At the same time, it is expressive enough to implement all required operations: All major database operators -including aggregation [24], selection [19], sorting [16,22,30,31], joins [20], hashing [2,3,14] and string operations [10] -, have been shown to be efficiently implementable within the constraints of the model. We therefore believe that the kernel programming model is a good choice to form the basis of a hardware-oblivious parallel database engine.…”

Section: The Kernel Programming Modelmentioning

confidence: 99%

“…Since Ocelot returns bitmaps, the runtime stays constant, while MonetDB has to materialize the list of qualifying oids, which gets more expensive as the result set grows. 10 We only measured range selections, as point selections use a hash selection in MonetDB, which Ocelot does not support yet.…”

Section: Microbenchmarksmentioning

confidence: 99%

Hardware-oblivious parallelism for in-memory column-stores

Heimel

Saecker²,

Pirk

et al. 2013

Proc. VLDB Endow.

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The multi-core architectures of today's computer systems make parallelism a necessity for performance critical applications. Writing such applications in a generic, hardware-oblivious manner is a challenging problem: Current database systems thus rely on laborintensive and error-prone manual tuning to exploit the full potential of modern parallel hardware architectures like multi-core CPUs and graphics cards. We propose an alternative design for a parallel database engine, based on a single set of hardware-oblivious operators, which are compiled down to the actual hardware at runtime. This design reduces the development overhead for parallel database engines, while achieving competitive performance to hand-tuned systems.We provide a proof-of-concept for this design by integrating operators written using the parallel programming framework OpenCL into the open-source database MonetDB. Following this approach, we achieve efficient, yet highly portable parallel code without the need for optimization by hand. We evaluated our implementation against MonetDB using TPC-H derived queries and observed a performance that rivals that of MonetDB's query execution on the CPU and surpasses it on the GPU. In addition, we show that the same set of operators runs nearly unchanged on a GPU, demonstrating the feasibility of our approach.

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GPU acceleration of finite state machine input execution: Improving scale and performance

Yaneva

Rajan

Dubach

2021

Software Testing Verif & Rel

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Model-based development is a popular development approach in which software is implemented and verified based on a model of the required system. Finite state machines (FSMs) are widely used as models for systems in several domains. Validating that a model accurately represents the required behaviour involves the generation and execution of a large number of input sequences, which is often an expensive and time-consuming process. In this paper, we speed up the execution of input sequences for FSM validation, by leveraging the high degree of parallelism of modern graphics processing units (GPUs) for the automatic execution of FSM input sequences in parallel on the GPU threads. We expand our existing work by providing techniques that improve the performance and scalability of this approach. We conduct extensive empirical evaluation using 15 large FSMs from the networking domain and measure GPU speed-up over a 16-core CPU, taking into account total GPU time, which includes both data transfer and kernel execution time. We found that GPUs execute FSM input sequences up to 9.28Â faster than a 16-core CPU, with an average speed-up of 4.53Â across all subjects. Our optimizations achieve an average improvement over existing work of 58.95% for speed-up and scalability to large FSMs with over 2K states and 500K transitions. We also found that techniques aimed at reducing the number of required input sequences for large FSMs with high density were ineffective when applied to all-transition pair coverage, thus emphasizing the need for approaches like ours that speed up input execution.

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iNFAnt

Cited by 78 publications

References 7 publications

Multi-Layer Packet Classification with Graphics Processing Units

Multi-Layer Packet Classification with Graphics Processing Units

Hardware-oblivious parallelism for in-memory column-stores

GPU acceleration of finite state machine input execution: Improving scale and performance

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