Indirect compensation techniques for three-stage CMOS op-amps

Saxena, Vishal; Baker, R. Jacob

doi:10.1109/mwscas.2009.5236164

Cited by 20 publications

(27 citation statements)

References 7 publications

(13 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Numerous compensation schemes for three stage amplifiers that alleviate the disadvantages of NMC have been proposed [33], [34], [35]. In all these works, the objective is to achieve sufficient PM and GBW with low values of compensation capacitance such that power efficiency is enhanced.…”

Section: Nested Miller Compensation For Three-stage Otasmentioning

confidence: 99%

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Harikumar

2014

Linköping Studies in Science and Technology. Thesis

View full text Add to dashboard Cite

In today's system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ √ Hz while consuming 6.8 mW.Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium r...

show abstract

Section: Nested Miller Compensation For Three-stage Otasmentioning

confidence: 99%

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Harikumar

2014

Linköping Studies in Science and Technology. Thesis

View full text Add to dashboard Cite

show abstract

“…However, they exhibit either complex implementation or larger power consumption when compared to the commonly used two-stage op-amps. This section provides a tutorial on the design techniques, introduced by the authors in [9], which result in high-speed, offset tolerant, and low power three-stage …”

Section: Indirect Compensation Of Three-stage Op-ampsmentioning

confidence: 99%

“…The PMOS diff-pair in second stage employs wider devices to increase the input common-mode range of the second stage. A split-length diff-pair (SLDP) is used for indirect compensation in order to achieve higher PSRR [9]. A diff-amp is used in the second stage to ensure that the third stage is correctly biased.…”

Section: B Three-stage Op-amp Compensationmentioning

confidence: 99%