Incremental reconfiguration of multi-FPGA systems

Lee, K. K.; Wong, D.F.

doi:10.1145/503048.503078

Cited by 7 publications

(4 citation statements)

References 12 publications

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“…Another method for compression of the reconfiguration bit stream which is suitable especially for the Xilinx XC6200 architecture has been described by Hauck et al [7]. For Multi FPGA systems it has been proposed by Lee and Wong [11] to perform the reconfiguration incrementally so that only parts of the FPGAs need to be reconfigured at the same time. A third approach is to use self-reconfigurability which means that the reconfiguration bits are computed directly on the chip so that they can be transferred faster to the system units that are reconfigured (see Köster and Teich [9], Sidhu et al [12], Wadhwa and Dandalis [16]).…”

Section: Introductionmentioning

confidence: 99%

Hyperreconfigurable architectures and the partition into hypercontexts problem

Lange

Middendorf

2005

Journal of Parallel and Distributed Computing

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Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increasing flexibility of modern dynamically reconfigurable systems improves their adaptability to computational needs but also makes fast reconfiguration difficult because of the large amount of reconfiguration information which has to be transferred. However, even when a computation uses this flexibility it will not use it all the time. Therefore, we propose to make the potential for reconfiguration itself reconfigurable. Such architectures are called hyperreconfigurable. Different models of hyperreconfigurable architectures are proposed in this paper. We also study a fundamental problem that emerges on such architectures, namely, to determine for a given computation when and how the potential for reconfiguration should be changed during run time so that the reconfiguration overhead is minimal. It is shown that the general problem is NP-hard but fast polynomial time algorithms are given to solve this problem for special types of hyperreconfigurable architectures. We define two example hyperreconfigurable architectures and illustrate the introduced concepts for corresponding application problems.

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Section: Introductionmentioning

confidence: 99%

Hyperreconfigurable architectures and the partition into hypercontexts problem

Lange

Middendorf

2005

Journal of Parallel and Distributed Computing

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“…Software applications include C++ compilation [8] and elaboration of scenario-based specifications [19]. Hardware applications include elaboration for VHDL simulation [1], reconfiguration of multi-FPGA systems [9], and compilation for parallel logic verification [17]. This paper further extends this technique to support run-time reconfigurable hardware designs.…”

Section: Background and Related Workmentioning

confidence: 99%

Incremental elaboration for run-time reconfigurable hardware designs

Derbyshire

Becker

Luk

2006

Proceedings of the 2006 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in application specific integrated circuits (ASICs) or microprocessors. These systems can often provide substantially more computational power than microprocessors and support higher flexibility than ASICs. The compilation of hardware during run time, however, can add significant runtime overhead to these systems. We introduce a novel compilation technique called incremental elaboration, which enables circuits to be dynamically generated during run time. We propose a set-based model for incremental elaboration, and explain how it can be used in the hardware compilation process. Our approach is illustrated by various designs, particulary those for pattern matching and shape-adaptive template matching.

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“…A principle problem of such architectures is that a high flexibility leads to a large amount of information required for reconfiguration (reconfiguration bit stream). Therefore, new approaches for dynamic reconfiguration have been proposed in the literature in the last years to cope with this problem: (1) off-line compression methods for the reconfiguration bit stream [1], (2) special hardware that allows to address a set of reconfiguration bits that receive the same value (an example is the wildcard mechanism of the Xilinx XC6200 [2]), (3) computation of the reconfiguration bits directly on the chip (see [3][4][5]), iv) performing the reconfiguration of Multi-FPGA systems incrementally ( [6]). Another concept is to adapt the actually available set of reconfigurable resources (and thus the number of reconfiguration bits that are necessary to define the state of the architecture during reconfiguration) to the actual needs during run time.…”

Section: Introductionmentioning

confidence: 99%

Design Aspects of Multi-level Reconfigurable Architectures

Lange

Middendorf

2007

J Sign Process Syst Sign Image

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Dynamically reconfigurable hardware has already been deployed for accelerating computationally demanding applications. Some of these hardware architectures allow run time reconfiguration but this usually leads to a large reconfiguration overhead. The advantage of run time reconfiguration is that it allows new algorithmic solutions for many applications. To study the potential of frequent run time reconfiguration it is interesting to investigate its costs and benefits from an abstract point of view and to develop new architectural concepts. Multilevel reconfigurable architectures are one such concept that introduces several levels of reconfiguration. This paper deals with new types of multi-level reconfigurable architectures. The corresponding problem of finding the best granularity for different reconfiguration levels is formulated and investigated. Although this problem is shown to be NP-complete, an interesting restricted subcase is solved optimally in polynomial time. For the general case, a good heuristic is proposed that is based on solutions for the restricted case. Results on three example applications show that the reconfiguration cost can be reduced with the new architectures. Based on a proposed measure of relative efficiency it is also shown that the new architectures are more efficient so that they obtain a larger reconfiguration cost reduction with less additional hardware.

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Incremental reconfiguration of multi-FPGA systems

Cited by 7 publications

References 12 publications

Hyperreconfigurable architectures and the partition into hypercontexts problem

Hyperreconfigurable architectures and the partition into hypercontexts problem

Incremental elaboration for run-time reconfigurable hardware designs

Design Aspects of Multi-level Reconfigurable Architectures

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