Hyperreconfigurable architectures and the partition into hypercontexts problem

Abstract

Dynamically reconfigurable architectures or systems are able to reconfigure their function and/or structure to suit the changing needs of a computation during run time. The increasing flexibility of modern dynamically reconfigurable systems improves their adaptability to computational needs but also makes fast reconfiguration difficult because of the large amount of reconfiguration information which has to be transferred. However, even when a computation uses this flexibility it will not use it all the time. Therefore, we propose to make the potential for reconfiguration itself reconfigurable. Such architectures are called hyperreconfigurable. Different models of hyperreconfigurable architectures are proposed in this paper. We also study a fundamental problem that emerges on such architectures, namely, to determine for a given computation when and how the potential for reconfiguration should be changed during run time so that the reconfiguration overhead is minimal. It is shown that the general problem is NP-hard but fast polynomial time algorithms are given to solve this problem for special types of hyperreconfigurable architectures. We define two example hyperreconfigurable architectures and illustrate the introduced concepts for corresponding application problems.

Multi-level reconfigurable architectures in the switch model

“…The test cases consist of reconfigurable designs implemented on the SHyRA architecture as described in [3]. The SHyRA architecture consists of a file of registers, a plane of LUTs, and a MUX and DeMUX that are used as interconnection for moving the data to the LUTs and the results back to the registers.…”

“…The formal model that we introduce in the following is an extension of the 2-level reconfigurable switch model as introduced in [3]. It should be noted that it is possible to extent other models of 2-level reconfigurable machines from [3].…”

“…For the switch model of reconfigurable architectures (which is the model used in this paper) the problem was called PHC-Switch. It has been shown in [3] that the PHC-Switch problem can be solved for 2-level reconfigurable architectures by dynamic programming in time O(n · m 2 ). For more general models of 2-level reconfigurable architectures the problem is NP-hard.…”

“…On the upper reconfiguration level the reconfiguration capabilities of the reconfigurable resources that are available for the lower level reconfiguration can be reconfigured. The upper level reconfiguration operations were called hyperreconfigurations in [3]. Accordingly there exist two types of (reconfiguration) contexts: i) the ordinary context is defined by the reconfiguration bits that have been loaded onto the architecture during the last reconfiguration operation and ii) the hypercontext is defined by the reconfiguration bits that have been loaded during the last hyperreconfiguration operation.…”

“…It has been argued in [3] that architectures with more than two reconfiguration levels might be advantageous to make dynamic reconfiguration even faster. But so far no detailed investigations have been done to explore the concept of multi-level reconfiguration for more than two levels of reconfiguration.…”