Incremental ABV for Functional Validation of TL-to-RTL Design Refinement

Abstract

Transaction-level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems. However, its introduction arouses a new challenge for designers and verification engineers, since there are no mature tools to automatically synthesize an RTL implementation from a transaction-level (TL) design, thus manual refinements are mandatory. In this context, the paper presents an incremental assertionbased verification (ABV) methodology to check the correctness of the TL-to-RTL refinement. The methodology relies on reusing assertions and already checked code, and it is guided by an assertion coverage metrics.

Automatic Fault Localization for SystemC TLM Designs

“…For instance, these include design methodologies [4], algorithms for design space exploration [5], [6] and verification approaches [7], [8], [9], [10], [11], [12], [13]. However, the existing debugging solutions for SystemC TLM have serious limitations (for a detailed discussion we refer to the related work section).…”

Proving transaction and system-level properties of untimed SystemC TLM designs

“…Methods commonly applied at TLM rely on simulation (see e.g. [5], [6], [7]) and therefore cannot guarantee the functional correctness. The existing formal verification approaches for SystemC TLM designs mainly check properties local to processes or have extremely high run-time (more details are discussed in the related work section).…”

Towards Equivalence Checking Between TLM and RTL Models

“…Some techniques have been proposed in the past to check the correctness of the topdown refinement flow [4,5]. In [4], properties expressed at TLM are reused at RTL by means of transactors.…”

“…Thus, the behavior expressed by the set of reusable properties can be checked also in the refined version of the design. In [5], an incremental verification based on assertions is proposed to validate the TLM-to-RTL design refinement. The concept of equivalence proposed in [4,5] is based on properties, i.e., two implementations are equivalent if they satisfy the same set of properties.…”

“…In [5], an incremental verification based on assertions is proposed to validate the TLM-to-RTL design refinement. The concept of equivalence proposed in [4,5] is based on properties, i.e., two implementations are equivalent if they satisfy the same set of properties. Thus, the effectiveness of such a kind of equivalence checking depends on the quality of the defined properties, since the equivalence is guaranteed only for behaviors for which a property has been defined.…”