Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis

Guzey, Onur; Wang, Li-C.; Levitt, Jeremy R.; Foster, Harry

doi:10.1109/tcad.2009.2034347

Cited by 8 publications

(4 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Focusing on the same area, research carried out in [18] filters tests that are highly likely to hit more coverage on an ALU DUT from a large pool of tests and exclude redundant tests to save simulation time. This is achieved by clustering.…”

Section: Stimulus and Test Generationmentioning

confidence: 99%

“…Other attempts incorporated additional different ML models such as Markov models and inductive logic programming to reach a faster coverage convergence rate [6][7][8]. More recent research in the domain of stimulus and test generation used a combination of supervised and unsupervised ML models such as neural networks, random forest and support vector machines to reduce the amount of needed input iterations and testcases to reach the planned coverage goals [9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. In the scope of coverage collection, there are studies that show improvements in both the runtime of simulations that capture coverage and the percentage of coverage reached, when either a supervised or unsupervised ML model is used [29][30][31].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Survey on Machine Learning Algorithms Enhancing the Functional Verification Process

Ismail¹,

Ghany

2021

Electronics

View full text Add to dashboard Cite

The continuing increase in functional requirements of modern hardware designs means the traditional functional verification process becomes inefficient in meeting the time-to-market goal with sufficient level of confidence in the design. Therefore, the need for enhancing the process is evident. Machine learning (ML) models proved to be valuable for automating major parts of the process, which have typically occupied the bandwidth of engineers; diverting them from adding new coverage metrics to make the designs more robust. Current research of deploying different (ML) models prove to be promising in areas such as stimulus constraining, test generation, coverage collection and bug detection and localization. An example of deploying artificial neural network (ANN) in test generation shows 24.5× speed up in functionally verifying a dual-core RISC processor specification. Another study demonstrates how k-means clustering can reduce redundancy of simulation trace dump of an AHB-to-WHISHBONE bridge by 21%, thus reducing the debugging effort by not having to inspect unnecessary waveforms. The surveyed work demonstrates a comprehensive overview of current (ML) models enhancing the functional verification process from which an insight of promising future research areas is inferred.

show abstract

Section: Stimulus and Test Generationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Survey on Machine Learning Algorithms Enhancing the Functional Verification Process

Ismail¹,

Ghany

2021

Electronics

View full text Add to dashboard Cite

show abstract

“…The authors in [1], [13] proposed a novel test detection framework where Support Vector Machine (SVM) one-class algorithm [14] is used to build models. The framework is limited to analyzing fixed-cycle functional tests.…”

Section: Introductionmentioning

confidence: 99%

Novel test detection to improve simulation efficiency

Chen

Sumikawa

Wang

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

Self Cite

View full text Add to dashboard Cite

Novel test detection is an approach to improve simulation efficiency by selecting novel tests before their application [1]. Techniques have been proposed to apply the approach in the context of processor verification [2]. This work reports our experience in applying the approach to verifying a commercial processor. Our objectives are threefold: to implement the approach in a practical setting, to assess its effectiveness and to understand its challenges in practical application. The experiments are conducted based on a simulation environment for verifying a commercial dual-thread low-power processor core. By focusing on the complex fixed-point unit, the results show up to 96% saving in simulation time. The main limitation of the implementation is discussed based on the load-store unit with initial promising results to show how to overcome the limitation.

show abstract

“…Directed simulation can then be used to cover corner test space at the end of the verification cycle. When using coveragebased verification, engineers typically want an estimate of the functional space covered and captured in quantifiable terms [103,134]. These include:…”

Section: Verification Methodsmentioning

confidence: 99%

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

Yang¹

View full text Add to dashboard Cite

Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis

Cited by 8 publications

References 13 publications

Survey on Machine Learning Algorithms Enhancing the Functional Verification Process

Survey on Machine Learning Algorithms Enhancing the Functional Verification Process

Novel test detection to improve simulation efficiency

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

Contact Info

Product

Resources

About