Increasing processor performance by implementing deeper pipelines

Abstract

One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between performance and pipeline depth using a Pentiurr~ 4 processor like architecture as a baseline and will show that deeper pipelines can continue to increase performance. This paper will show that the branch misprediction latency is the single largest contributor to performance degradation as pipelines are stretched, and therefore branch prediction and fast branch recovery will continue to increase in importance. We will also show that higher performance cores, implemented with longer pipelines for example, will put more pressure on the memory system, and therefore require larger on-chip caches. Finally, we will show that in the same process technology, designing deeper pipelines can increase the processor frequency by 100%, which, when combined with larger on-chip caches can yield performance improvements of 35% to 90% over a Pentium@ 4 like processor.

Cost effective physical register sharing

“…This is not the case for 16-and 8-bit moves. takes place, an entry is allocated in a structure, the Multiple Instantiation Table (MIT), which has only a few entries (e.g., 8). We will describe the MIT in more details in Section 4…”

“…For instance, per-register counters cannot be checkpointed, by construction. This is problematic since the branch misprediction recovery latency has been shown to strongly contribute to deeply pipelined processors performance [8]. As a result, there is a call for a sharing scheme that would allow such a simple recovery process for the renamer state.…”

“…In deeply pipelined architectures, the branch misprediction penalty has been shown to be the largest contributor to performance degradation [8].…”

Power-performance of multi-threaded multi-core processor: Analysis, optimization and simulation

“…Kunkel and Smith [6], first studied the optimum pipeline depth and performance metric. Recently, many authors revisited this with performance only metric [2] [4] [7]. As the power becomes the main constraint for the recent processor design, we need to consider the best design for performance with little power sacrifice and appropriate power/perfromance metric.…”

The Midlifekicker Microarchitecture Evaluation Metric

“…This is close to our expectation for the pipeline overhead (the constant overhead delay). To confirm our assumption, we refer to the numbers presented in [11]. First, the authors confirm the 125 ps pipeline overhead using a standard design flow and .18µm technology.…”