Increased memory performance during vector accesses through the use of linear address transformations

Harper, D. T.

doi:10.1109/12.123399

Cited by 29 publications

(28 citation statements)

References 12 publications

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“…The drawback of these systems is the modulo operation on prime numbers which is difficult to implement efficiently in hardware. An example of the second category is represented by the skewing memory systems including the widely used row rotation schemes and XOR schemes [18][19][20][21][22][23][24].…”

Section: Background and Related Workmentioning

confidence: 99%

High-bandwidth Address Generation Unit

Galuzzi

Gou

Calderón

et al. 2008

J Sign Process Syst Sign Image Video Technol

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In this paper we present an efficient data fetch circuitry to retrieve several operands from a n-way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data structures of arbitrary lengths and different odd strides. The experimental results show that our address generation unit is capable of generating eight 32 − bit addresses every 6 ns for different strides when implemented on a VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using only trivial hardware resources.

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Section: Background and Related Workmentioning

confidence: 99%

High-bandwidth Address Generation Unit

Galuzzi

Gou

Calderón

et al. 2008

J Sign Process Syst Sign Image Video Technol

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“…Row rotation schemes [7] with N=2 n was used. Another Harper_s approach concerning arbitrary stride accesses utilizes XOR-schemes [16]. XOR-schemes allow simpler computation since merely logic gates are demanded and no carry bits are used for computation [8,43].…”

Section: Arbitrary Stride Accessmentioning

confidence: 99%

“…However, CPMA is relatively complex architecture to be used only for stride accesses. A more dedicated memory system for changeable constant stride access utilizes dynamic storage schemes that allow multiple stride specific schemes to be used within a single system [15,16]. Nevertheless, the memory module count is restricted to a power of two and only interleaved memory system is considered in [15] and [16].…”

Section: Introductionmentioning

confidence: 99%

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Configurable Data Memory for Multimedia Processing

Aho

Vanne

Hämäläinen

2007

J Sign Process Syst Sign Image

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In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the accessed data element count equals to the number of memory modules. Timing and area estimates are given for Altera Stratix FPGA and 0.18 micrometer CMOS process with memory module count from 2 to 32. The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectively. The complexity of the proposed system is shown to be a trade-off between application specific and highly configurable parallel memory system.

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“…To cope with bank conflicts of vector access across stride families, several techniques have been proposed, including the use of buffers [24], dynamic memory schemes [25][26][27][28], memory modules clustering [24], and intra-stream out-oforder access [29], just to name a few. Some of the existing techniques may be complementary to our Elastic Pipeline proposal, however subject to certain limitations.…”

Section: Related Workmentioning

confidence: 99%

Addressing GPU On-Chip Shared Memory Bank Conflicts Using Elastic Pipeline

Gou

Gaydadjiev

2012

Int J Parallel Prog

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One of the major problems with the GPU on-chip shared memory is bank conflicts. We analyze that the throughput of the GPU processor core is often constrained neither by the shared memory bandwidth, nor by the shared memory latency (as long as it stays constant), but is rather due to the varied latencies caused by memory bank conflicts. This results in conflicts at the writeback stage of the in-order pipeline and causes pipeline stalls, thus degrading system throughput. Based on this observation, we investigate and propose a novel Elastic Pipeline design that minimizes the negative impact of on-chip memory bank conflicts on system throughput, by decoupling bank conflicts from pipeline stalls. Simulation results show that our proposed Elastic Pipeline together with the co-designed bank-conflict aware warp scheduling reduces the pipeline stalls by up to 64.0 % (with 42.3 % on average) and improves the overall performance by up to 20.7 % (on average 13.3 %) for representative benchmarks, at trivial hardware overhead.

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Increased memory performance during vector accesses through the use of linear address transformations

Cited by 29 publications

References 12 publications

High-bandwidth Address Generation Unit

High-bandwidth Address Generation Unit

Configurable Data Memory for Multimedia Processing

Addressing GPU On-Chip Shared Memory Bank Conflicts Using Elastic Pipeline

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