Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test sets

Fritzemeier, R.R.; Soden, J.M.; Treece, R.K.; Hawkins, C.F.

doi:10.1109/test.1990.114051

Cited by 55 publications

(30 citation statements)

References 13 publications

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“…Simple testability metrics for single line controllability are sufficient to tell us how well IODQ might be used to test for stuck-at faults, since each net need only be toggled to 0 and 1 values for 100% stuck-at fault test coverage [7]. However, more complex measures are required to ascertain a circuit's IDI~Q testability under the leakage fault model assumption.…”

Section: Controllability Calculationmentioning

confidence: 99%

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ITA: An algorithm for I DDQ testability analysis

McNamer

Nagle

1996

J Electron Test

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This paper presents the IDDQ Testability Analysis (ITA) algorithm for the estimation of a circuit design's leakage fault testability. The algorithm is based on the calculation of the probability of applying each of a set of "essential vectors" to each gate in the circuit. The essential vectors for each gate represent the minimal vector set that provides maximal leakage fault coverage.ITA assumes independence of circuit net values, except in the case of reconvergent fanout. Reconvergent fanout is identified by "levetizing" the circuit and propagating sets of labels from the primary inputs forward through the circuit, beginning with unique labels (integers) on each primary input. ITA evaluation of reconvergent fanout points then uses a backward implication procedure to calculate the essential vector probability values for the reconvergent gate, except in the case where backward implication is not deterministic.Results of an implementation of ITA are presented for a set of benchmark circuits, including a sample of the ISCAS '85 and ' 89 circuits.

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Section: Controllability Calculationmentioning

confidence: 99%

“…IDDQ testing has been shown to be an effective complement to standard stuck-at fault testing due to its ability to detect many of those defects that are not correctly modeled as stuck-at faults [6][7][8][9][10]. Moreover, elevated Iix~e has been shown to be a reliability hazard even when a device passes functional testing.…”

Section: Introductionmentioning

confidence: 99%

ITA: An algorithm for I DDQ testability analysis

McNamer

Nagle

1996

J Electron Test

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“…In IDDQ testing, as in logic testing, stuck-at faults (SAF) have been often considered [1,11,20,33]. Kondo and Cheng have classied SAFs into the following three types based on the logical behavior of the fault [20].…”

Section: F Ault Modelmentioning

confidence: 99%

Fault models and test generation for IDDQ testing

Higami

Takamatsu²,

Saluja³

et al.

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

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Abstract| This paper surveys recent research related to IDDQ testing, particularly focuses on fault models and test generation methods.(1) The paper provides a taxonomy of fault models that have been studied in literature, and classies these models into a small set of faults.(2) The paper describes ecient test generation methods and fault simulation methods. Test compaction methods, including reduction of the total number of test vectors and selection of IDDQ measurement v ectors, are also described.

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“…Until now, it is shown that supply current testings, especially the IDDQ testing for CMOS circuits, are very useful for realizing high reliable systems [ 1,2,3]. In order to detect faults, the IDDQ testing utilizes the property that if any defects do not occur in CMOS circuits, the extremely less supply current has appeared.…”

Section: Introductionmentioning

confidence: 99%

“…That is, in the process of the IDDQ testing, faults must be sensitized, like in fault detection methods based on primary output logic values, but the effects of the faults do not have to be always propagated to any primary outputs, because faults can be detected by the IDDQ testing if any effects of faults are generated in the supply current. By using this property to detect single stuck-at faults in CMOS circuits, a fault simulation algorithm can be simplified, the size of test vectors can be reduced and the fault coverage can be increased [3]. Also, it is reported that the IDDQ testing can detect some of redundant faults, which can not be detected by measuring the output logic values [5].…”

Section: Introductionmentioning

confidence: 99%

Test input vectors for supply current testing of TTL combinational circuits

Hashizume

Tamesada

Tsukimoto

Proceedings First Asian Test Symposium (ATS `92)

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In this paper, test input vectors for ISCAS-85 benchmark circuits are derived, with which single faults of each signal line in the lTL combinational circuits can be detected by their quiescent supply currents. Also, they are compared with the vectors for fault detection methods based on the primary output logic values. It is shown that by detecting faults with supply currents of T7z circuits, smaller size of test inputs can be derived for most of the circuits than fault detection methods based on the primary output logic values, and ako, if both the output logic values and the supply current are used for detecting faults, the number of the test inputs can be reduced.

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Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test sets

Cited by 55 publications

References 13 publications

ITA: An algorithm for I DDQ testability analysis

ITA: An algorithm for I DDQ testability analysis

Fault models and test generation for IDDQ testing

Test input vectors for supply current testing of TTL combinational circuits

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