Incorporation of direct current superposition as a means for high quality contact and slotted contact structures utilizing litho-freeze-litho-etch

Smith, J.H.; Villiers, Anton de; Mohanty, Nihar; Miyata, Yuichiro; Fulford, Daniel

doi:10.1109/asmc.2014.6846959

Cited by 3 publications

(2 citation statements)

References 2 publications

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“…Since the early 2000s, in the face of rising lithography costs and delayed capabilities, alternative patterning solutions have enabled device scaling for advanced nodes and helped maintain time to market. Examples of such patterning techniques include LFLE 4 , self-aligned double patterning (SADP) 5 , and spacer-assisted litho-etch-litho-etch (SALELE) 6 . While these techniques produce self-aligned pitch split patterns, spacer-based techniques such as SADP and SALELE require the deposition and etch of materials which reduce throughput and increase manufacturing costs.…”

Section: Introductionmentioning

confidence: 99%

Sub-20nm tip-to-tip enabled by anti-spacer patterning

Grzeskowiak,

Murphy,

Power

et al. 2024

Advances in Patterning Materials and Processes XLI

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Alternative patterning solutions, such as litho-freeze-litho-etch (LFLE) and spacer-based pitch splitting, have been a cornerstone of advanced technology nodes to enable device scaling. The greatest utility comes from the ability to self-align a pitch splitting process; however, traditional spacer-based patterning techniques require the deposition and etch of multiple materials, which reduce throughput and increase manufacturing costs. Anti-spacer technology, on the other hand, enables both self-aligned pitch splitting and high throughput via a single pass track-based process. Here, we present the utility of combining a 193 nm immersion anti-spacer process with LFLE to enable the formation of sub-20 nm slot contact features for a minimum tip-to-tip cut, with a scaling path to achieve sub-12 nm cuts.

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Section: Introductionmentioning

confidence: 99%

Sub-20nm tip-to-tip enabled by anti-spacer patterning

Grzeskowiak,

Murphy,

Power

et al. 2024

Advances in Patterning Materials and Processes XLI

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show abstract

“…1,2) In recent years, there has been significant interest in augmenting multifrequency CCP sources with the superposition of high negative direct current (dc) voltage (∼100 s of V to >1 kV negative) on electrodes opposing wafers in capacitive discharges (DC superposition or dc/rf hybrid) for etching applications. 3,4) Generally the dc biased electrode opposing a wafer is referred to as a "top" electrode while the electrode on which a semiconductor wafer being processed sits is referred to as the "bottom" electrode. A very high frequency may or may not be applied at top electrode.…”

Section: Introductionmentioning

confidence: 99%

Simulations of hybrid direct current radiofrequency (dc/rf) capacitively coupled plasmas

Ranjan¹,

Ventzek²

2019

Jpn. J. Appl. Phys.

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Effects of applying a high negative direct current (dc) voltage in argon capacitive coupled plasmas on the flux of secondary electrons (SEs) to a radiofrequency (rf) biased electrode and plasma uniformity were investigated using particle-in-cell Monte Carlo collision simulation and results were compared with experimental results. High energy SEs originating at electrodes with high negative dc voltage due to ion-impact as well as electron-impact were accelerated out of the sheath through the sheath voltage drop. These SEs gain energy equal to the applied dc voltage and either travel to the wafer electrode where they are lost (dumped) or are trapped between electrodes depending on the voltage on bottom electrode. Trapping and dumping of ballistic electrons depends on the magnitudes of the voltages (dc and rf) applied to each electrode. High energy SEs alter the electron energy distribution function at the wafer, high energy electron flux to the wafer and the plasma density profile. With the application of negative dc voltage, wafer receives high energy electron flux with energies up to applied dc voltage. For the range of conditions examined in this paper, the plasma density increases with the application of the negative dc voltage due to ionization by trapping of high energy SEs. The electrons that originate at the negative dc electrode minimize the impact of enhanced radial electric fields at the rf electrode edge allowing dc/rf plasmas to be center peaked even at low (13.56 MHz) rf frequencies.

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The line edge roughness improvement with plasma coating for 193nm lithography

Zheng

Zhang

2017

2017 China Semiconductor Technology International Conference (CSTIC)

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Incorporation of direct current superposition as a means for high quality contact and slotted contact structures utilizing litho-freeze-litho-etch

Cited by 3 publications

References 2 publications

Sub-20nm tip-to-tip enabled by anti-spacer patterning

Sub-20nm tip-to-tip enabled by anti-spacer patterning

Simulations of hybrid direct current radiofrequency (dc/rf) capacitively coupled plasmas

The line edge roughness improvement with plasma coating for 193nm lithography

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