Incorporating boundary scan tools in PXI based ATE systems

Ehrenberg, H.; Wenzel, Thomas; Trier, M.

doi:10.1109/autest.2003.1243558

Cited by 5 publications

(3 citation statements)

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“…Furthermore, some circuit nodes connecting two or more BGA (Ball Grid Array) pins may never have surface to test so it makes boundary scan the only way of quality testing [13]. [14].…”

Section: Introductionmentioning

confidence: 99%

A novel method for diagnosis of board level interconnect faults using boundary scan

Kumar

Sharma

et al. 2010

2010 International Conference on Computer and Communication Technology (ICCCT)

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Over the past years complexity of PCB board and the surface mount technology has increased by leaps and bounds. This limits the use of traditional in-circuit test techniques for testing of such boards. This paper addresses the various issues of board level interconnect testing using Boundary Scan architecture. This work implements BIST using Boundary Scan technique. A new Algorithm is developed to diagnose PCB level faults. The dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults are taken up in this paper. The proposed algorithm is also compared with the existing algorithms viz modified counting, walking one's algorithm and others. Our results are found to be better than the existing algorithms.

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“…Furthermore, some circuit nodes connecting two or more BGA (Ball Grid Array) pins may never have surface to test so it makes boundary scan the only way of quality testing [13]. [14].…”

Section: Introductionmentioning

confidence: 99%

A novel method for diagnosis of board level interconnect faults using boundary scan

Kumar

Sharma

et al. 2010

2010 International Conference on Computer and Communication Technology (ICCCT)

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“…Boundary scan itself cannot do quality testing of complete PCB. For enhancing the PCB-level testing, other testing methods such as in-circuit test, functional test and manufacturing defect analyzer are also used (Ehrenberg et al, 2007). In addition to these, other techniques are I DDQ and scan based (Sharma et al, 2011).…”

Section: Introductionmentioning

confidence: 99%

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Sharma¹,

Sharma

Kaushik

et al. 2011

Circuit World

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Purpose -This paper aims to address the various issues of board-level (off-chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off-chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted. Design/methodology/approach -The problems in board-level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board-level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique. Findings -The dominant-1 (wired-OR, denoted as WOR), dominant-0 (wired-AND, denoted as WAND) and stuck-at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms.Research limitations/implications -The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults. Practical implications -The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors. Originality/value -Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board-level dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults. The proposed algorithm is completely free from aliasing and confounding syndromes.

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“…Aerospace, Automotive, Military, Telecom, and Consumer Electronics), Industrial Test and Automation are the main applications for PXI today. [1] PCI eXtensions for Instrumentation (PXI) is the open, multi-vendor standard for measurement and automation that delivers more than 10 times the performance of older measurement and automation architectures. With PXI, you automatically benefit from the low cost, ease of use, modularity, and flexibility of PC technology.…”

Section: Introduction To Pximentioning

confidence: 99%

Advancing ate systems with PXI based power-off diagnostic instrument technology

Howard¹,

Haltiner²

IEEE Autotestcon, 2005.

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Typical military and aerospace power-on parametric or functional CCA tests reduce a failure to a cluster or ambiguity group of components. Adding PXI based power-off diagnostics validates detection and isolation of faulty components beyond the detailed parametric or functional testing and fault isolation of the test. Replacing the diagnostics portion of the test with power-off diagnostics allows reduced development time, enhanced fault isolation, while allowing the existing test to perform "Ready for Issue" verification. These existing tests assume that the defective Unit Under Test (UUT) can accept power. If the UUT can not accept power, the PXI based power-off diagnostics allows diagnosis of those UUTs. Automating probing during the diagnostics increases productivity and accuracy. This COTS PXI based approach maximizes the diagnostic capability while lowering ambiguity levels for component level faults as well as decrease the total cost of test development.

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Incorporating boundary scan tools in PXI based ATE systems

Cited by 5 publications

References 0 publications

A novel method for diagnosis of board level interconnect faults using boundary scan

A novel method for diagnosis of board level interconnect faults using boundary scan

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Advancing ate systems with PXI based power-off diagnostic instrument technology

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