Including the Effects of Process-Related Variability on Radiation Response in Advanced Foundry Process Design Kits

Characterizing, modeling, and simulating soft error susceptibility in cell-based designs in highly scaled technologies

“…Moreover, many researchers have reported pulse broadening effects during pulse propagation and its dependencies on active loading (fan-out) and passive loading (interconnect) of the target circuits [6], which requires the test chip to include the corresponding loading variance on the target circuits. In order to be compatible with the foundry model enhancement approach, test circuits should be suitable to include other radiation effects such as total ionizing dose effects [7], as mitigating SETs is not the only enhancements that must be performed for space applications. To address the above challenges, a dual channel PMC was designed and implemented.…”

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

“…It is reported that although several scaled down technologies are inherently rather radiation hard from a viewpoint of total ionizing dose (TID) damage, the statistical behavior of the radiation degradation should surely not be neglected (5)(6). This has a direct impact on the use of 'commercial-off-the shelf (COTS)' electronic components for space applications (7), as superimposed on the statistical variability one has to take into account the radiation-induced variability.…”

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

“…Space applications using advanced CMOS technologies require accurate evaluation of the variability of total-ionizing dose (TID) response and its dependence on individual device layout [1]. Device-to-device variability between nominally identical devices and systematic variability that depends on the local structure can affect circuit-level degradation [1,2].…”

“…Device-to-device variability between nominally identical devices and systematic variability that depends on the local structure can affect circuit-level degradation [1,2]. As the technology scales, the pre-irradiation off-state (V g = 0) current mechanisms can change from being dominated by junction or sidewall leakage to being dominated by channel subthreshold current.…”

“…Post-irradiation off-state leakage current is usually a result of radiation-induced oxide trapped charge in the shallow trench isolation (STI), which can invert the p-substrate in nMOS transistors at the STI edges, thereby creating a leakage path between the drain and source [3][4][5][6]. In [1] it was shown that the standard deviation of the off-state leakage current increases with TID for devices with a particular threshold-voltage variant (low V t , or LVT) from a 90 nm technology, and in [7] the effect of channel width on TID-induced leakage current is investigated for the LVT devices from the same 90 nm technology. Here we compare the impact of device width on the variability in pre-and post-irradiation off-state current in both 90 nm and 65 nm nMOS devices for three different threshold-voltage variants.…”