In_0.53Ga_0.47As-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors Utilizing Y₂O₃ Buried Oxide

Abstract

In this letter, we have investigated electrical properties of metal-oxide-semiconductor (MOS) gate stack of Pt/Y 2 O 3 /In 0.53 Ga 0.47 As under different annealing conditions. We have found that proper annealing step significantly improves MOS interfacial properties of Pt/Y 2 O 3 /In 0.53 Ga 0.47 As MOS capacitors. Finally, we have realized MOS interface with a low density of trap state ( D it ) of 4 × 10 12 eV −1 · cm −2 and hysteresis of 15 mV using postmetallization annealing at 350°C. Furthermore, we also first demonstrated In 0.53 Ga 0.47 As-on-insulator (-OI) transistors with Y 2 O 3 buried oxide layer using developed MOS interface. Fabricated In 0.53 Ga 0.47 As-OI transistors show good I-V characteristics and high peak mobility of ∼2000 cm 2 /Vs. Index Terms-InGaAs MOSFETs, III-V MOSFETs, InGaAs-OI, wafer bonding, III-V compound semiconductor.

3D Stackable Synaptic Transistor for 3D Integrated Artificial Neural Networks

“…We measured the transfer characteristics of the synaptic transistor for various V BG bias, as shown in Figure a. We applied the same bias range as the measurement method of hysteretic characteristics in Figure a, and the gate electrode was swept forward from −3 to 5 V with the application of V BG bias from −0.8 to 0.4 V and a voltage step of 0.1 V. The threshold voltages of the transfer curves in In 0.53 Ga 0.47 As synaptic transistors were shifted with respect to changing V BG , which is a unique advantage of the In 0.53 Ga 0.47 As-OI structure Figure b shows conductance characteristics in potentiation and depression with a V BG of −0.6 V. We obtained impressive performance improvement by biasing V BG (see Figure S5, Supporting Information for details).…”

“…Here, the substrate etching process can be changed to an epitaxial lift-off process to reduce the cost by reusing the donor substrate , (in Figure S1, Supporting Information for details). An innovative development was the introduction of the direct wafer bonding (DWB) technique for substrates based on M3D integration as the DWB technique allows transfer of single crystalline device layers without defects. − Subsequently, synaptic transistors were fabricated using an In 0.53 Ga 0.47 As-OI substrate by the gate last process using Al 2 O 3 /HfO 2 /Al 2 O 3 /Pt gate stack as a weight storage layer (in Figure S2, Supporting Information for detail). Here, the maximum process temperature was 300 °C for the device fabrication, indicating our device fabrication was highly compatible with 3D integration .…”

Octopus‐Inspired Smart Adhesive Pads for Transfer Printing of Semiconducting Nanomembranes

“…The maximum values of mobility and on/off current ratio are ≈3000 cm 2 V −1 s −1 and 5.3 × 10 3 (averages: ≈2026 cm 2 V −1 s −1 and 4 × 10 3 ), respectively. To the best of our knowledge, this mobility is the largest among heterogeneously integrated InGaAs FETs on Si substrates with top‐ or bottom‐gate structures (see Table S2, Supporting Information). These results of high electron mobility and on/off current ratio indicate the excellent electronic quality of the transferred InGaAs layer and the efficiency of the transfer printing via the suggested octopus‐inspired smart adhesive system.…”

High-${k}$ HfO2-Based AlGaN/GaN MIS-HEMTs With Y2O3 Interfacial Layer for High Gate Controllability and Interface Quality

“…In this work, high-k Y 2 O 3 with ultra-low oxygen permeability, high bonding strength and high thermodynamic robustness has been adopted as the buried layer (1nm) under the 12 nm HfO 2 [11]- [13]. Correspondingly, GaN MIS-HEMT has obtained a gate leakage as low as ∼10 −12 A/mm.…”