In-Situ Delayering in Atomic Force Microscope for Sub-20nm Technology Devices

Yap, Matthew H. T.; Wei, Teo Chea; Narang, Vinod

doi:10.1109/ipfa.2018.8452590

2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2018

DOI: 10.1109/ipfa.2018.8452590

|View full text |Cite

In-Situ Delayering in Atomic Force Microscope for Sub-20nm Technology Devices

Matthew H. T. Yap¹,

Teo Chea Wei²,

Vinod Narang³

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2022

Publication Types

Select...

Article1

Relationship

Self Cite0

Independent1

Authors

Journals

Cited by 1 publication

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview

2022

View full text Add to dashboard Cite

Microprocessors use static random-access memory (SRAM) cells in the cache memory design. As a part of the central computing component, their performance is critical. Modern system-on-chips (SoC) escalate performance pressure because only 10–15% of the transistors accounts for logic, while the remaining transistors are for the cache memory. Moreover, modern implantable, portable and wearable electronic devices rely on artificial intelligence (AI), demanding an efficient and reliable SRAM design for compute-in-memory (CIM). For performance benchmark achievements, maintaining reliability is a major concern in recent technological nodes. Specifically, battery-operated applications utilize low-supply voltages, putting the SRAM cell’s stability at risk. In modern devices, the off-state current of a transistor is becoming comparable to the on-state current. On the other hand, process variations change the transistor design parameters and eventually compromise design integrity. Furthermore, sensitive information processing, environmental conditions and charge emission from IC packaging materials undermine the SRAM cell’s reliability. FinFET-SRAMs, with aggressive scaling, have taken operation to the limit, where a minute anomaly can cause failure. This article comprehensively reviews prominent challenges to the SRAM cell design after classifying them into five distinct categories. Each category explains underlying mathematical relations followed by viable solutions.

show abstract

SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview

2022

View full text Add to dashboard Cite

show abstract

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

hi@scite.ai

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

In-Situ Delayering in Atomic Force Microscope for Sub-20nm Technology Devices

Cited by 1 publication

References 3 publications

SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview

SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview

Contact Info

Product

Resources

About