In-Situ Characterization of High-Speed I/O Chip-Package Systems

Ahn, Jahyun; Puligundla, Sudeep; Bashirullah, Rizwan; Fox, R.M.; Eisenstadt, W.R.

doi:10.1109/epep.2007.4387189

Cited by 5 publications

(1 citation statement)

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“…In 2-D ICs, characterization techniques for high-speed I/O have been developed. Example techniques use random-jitter injection [3] and methods of signal integrity model validation for highspeed IO chip-package systems [4] that compare IBIS macro model based SPICE simulations and on-board measurements. In-situ characterization and verification becomes critical in 3D stacked ICs.…”

Section: Introductionmentioning

confidence: 99%

GTL high speed I/O in 3D ICs for TSV and interconnect signal integrity characterization

Baek

Harb

Eisenstadt

2012

2012 IEEE 62nd Electronic Components and Technology Conference

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This paper focuses on TSV and interconnect signal integrity characterization of 3D IC embedded test structures that measure GTL high speed I/O performance. The three Tiers of a CMOS 3D IC were fabricated by MIT Lincoln Laboratory in a 150nm SOI process bonded together and the test structures were ball-bonded on to a custom FR-4 board designed for matched 50Ω microwave and high speed transient measurements. The comparison between on-chip and FR-4 board measurement results for TSV and interconnect signal integrity characterization will be shown and analyzed using equivalent electrical models. In addition, the paper reports extensive additional on-board measurements including, 1) 3D IC GTL I/O response to varying data patterns, 2) Edge timing comparing GTL signals launched from several 3D IC Tiers simultaneously to the same I/O output, and 3) GTL I/O performance under degraded environmental conditions in the 3D IC such as reduced bias.

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Section: Introductionmentioning

confidence: 99%