In-orbit experiment on the fault-tolerant space computer aboard the satellite Hiten

Takano, Tadashi; Yamada, Tetsuya; Shutoh, K.; Kanekawa, Nobuyasu

doi:10.1109/24.556585

Cited by 8 publications

(3 citation statements)

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“…In the implementation for this class of codes, t parity check bits are added to the unprotected information by encoding the t-distance interleaved bits to detect t-bit burst errors [22]. In this case, more memory cells in each cache line can be saved by using the proposed CTDP scheme because more parity bits are needed for tags and data in the separate parity protection schemes; so, the overhead reduction ratio is the same as that given previously in equation (1).…”

Section: Extension For Stronger Codesmentioning

confidence: 99%

“…HE protection of storage systems such as memories against soft errors (caused by phenomena such as Single Event Upsets (SEUs)) has been widely studied in the technical literature; these errors can lead to data corruption and in some cases even to a system failure [1]- [4]. Error detection and correction codes (EDCCs) initially applicable to errors in data transmission are also commonly used to protect memories (including both conventional CMOS memories [5], [6] and emerging next-generation memories based on alternative technologies [7], [8]) in the presence of soft errors.…”

Section: Introductionmentioning

confidence: 99%

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Protection of Associative Memories Using Combined Tag and Data Parity (CTDP)

Liu

Reviriego

Lombardi

2021

IEEE Trans. Nanotechnology

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As emerging memories are utilized in processors as main memory, they must also coexist with CMOS memories; for instance SRAMs, are used to implement smaller, but faster associative memories. These hybrid designs exploit the advantages of both types of memories to achieve better performance. For some applications, the improvement in performance for on-chip associative memories is crucial for the overall computing system. For CMOS memories, soft errors are a major concern because they flip bits and can lead to data corruption and even a system failure. Error Detection and Correction Codes (EDCCs) are commonly used to protect memories against soft errors. In associative memories, an entry is formed by a tag and its associated data (or value). EDCCs are typically used to separately protect the tag and the data. This paper considers the protection of associative memories in which false negatives do not cause a failure. A Combined Tag and Data Parity (CTDP) protection scheme is proposed. This new approach utilizes a single parity bit per entry, so it reduces the number of parity bits needed to protect an entry as well as the memory size. The proposed scheme also reduces the complexity of read operations; it incurs the lowest circuit overhead for the protection circuitry in terms of area, delay and power consumption when compared to other schemes found in the technical literature. This makes the proposed scheme germane to associative memories used in hybrid designs that combine SRAMs and emerging memories. The extension of the proposed scheme to stronger codes is also discussed.

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Section: Extension For Stronger Codesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Protection of Associative Memories Using Combined Tag and Data Parity (CTDP)

Liu

Reviriego

Lombardi

2021

IEEE Trans. Nanotechnology

View full text Add to dashboard Cite

show abstract

“…Nonparametric methods based on voting have been applied widely in reliability problems. An example is their use to achieve fault tolerance in satellite systems (Takano et al 1996). Other applications include voting-based algorithms such as the Hough transform (see, for example, Duda and Hart 1973).…”

Section: Introductionmentioning

confidence: 99%