Fault-Tolerant System Technology

Kanekawa, Nobuyasu; Ibe, Eishi; Sügimura, Takashi; Uematsu, Yutaka

doi:10.1007/978-1-4419-6715-2_5

Cited by 1 publication

(3 citation statements)

References 13 publications

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“…With conventional design methods [12]- [15], [19], (b-1) and (b-2) are easily embeddable in an FPGA; however, (b-3) is insufficient. Regarding (b-3), the issues with implementing comparators in FPGAs are as follows.…”

Section: B Proposed Design Methods Of Tsc Comparators Implementable O...mentioning

confidence: 99%

“…An example of a TSC LSI architecture is shown in Fig. 1 [14], [15], [19]. Two n-bit inputs (a 0 -a n−1 and b 0 -b n−1 ) from both dual-modular redundancy (DMR) functional blocks A and B are compared in this TSC comparator.…”

Section: A Tsc and Tsc Comparator (Related Work)mentioning

confidence: 99%

“…Therefore, intrachip redundancy is commonly used for achieving dependability [12], [13]. Totally selfchecking (TSC) comparators with an online fault injection method for intrachip redundancy were proposed [14], [15]. These TSC comparators can conduct self-diagnosis without any modification in the functional blocks, i.e., applying encoding such as error-correction code (ECC), to the functional block.…”

mentioning

confidence: 99%

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Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs

Kanno

Toba

Shimamura

et al. 2020

IEEE Trans. VLSI Syst.

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In this article, we propose a method for designing online totally self-checking (TSC) comparators for TSC systems implementable on field-programmable gate arrays (FPGAs). This method can be used to conduct exhaustive online diagnostics of each lookup table (LUT), which involves mapping the fundamental components of the comparator, with a small number of test patterns by directly measuring output of each LUT. Our method drastically reduces the number of test patterns for exhaustive diagnosis on the order of the input number n [O(n)] (n is the input number to the comparator) while maintaining 100% coverage, even if we only know the specifications of the LUT without knowing its detailed structure. FPGAs will be easily applicable to systems that require high dependability. To confirm the soft error rate (SER) in a static random-access memory (SRAM)-based FPGA, we also conducted an experiment involving a single-event upset (SEU) caused by neutron radiation. For this experiment, we designed an FPGA implementation of 1575 identical dual-modular-redundant TSC comparators. The experiment was conducted for 10.4 h, and 34 errors were observed regarding such failures in comparator function. The evaluated SER for the TSC comparator with the proposed method was 0.055 FIT at sea level of New York City.

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Section: B Proposed Design Methods Of Tsc Comparators Implementable O...mentioning

confidence: 99%

Section: A Tsc and Tsc Comparator (Related Work)mentioning

confidence: 99%