In-Memory Computing: The Next-Generation AI Computing Paradigm

Ma, Yufei; Du, Yuan; Du, Li; Lin, Jun; Wang, Zhongfeng

doi:10.1145/3386263.3407588

“…The additional NOR gate is used between two sense amplifiers (SA3 and SA4) to perform the XOR operation of C and D, as shown in Figure 12(a). To perform a boolean logic operation between C and D, WWL [2] and WWL [3] are activates simultaneously, which seems scenario similar to C6T, and there is the chance for compute-disturbance. Figure 14[a-b] shows a 1K Monte-Carlo simulation result of compute-disturbance versus varied write word line(WWL) activation time.…”

Section: A In Memory Boolean Computationmentioning

confidence: 99%

“…When WWL is turned on for 300ps, compute-disturbance occurs, and 16.6% of data is flipped, as shown in Figure 14(b). In proposed IMC architecture, WWL [2] and WWL [3] are activated for the duration of 200ps for reliable sensing(no-compute-disturbance) of boolean logics [28].…”

Section: A In Memory Boolean Computationmentioning

confidence: 99%

“…It is observed from Figure 15, the row[0] data match with the search data string; as a result, ML[0] will remain at precharged value VDD, and the sense amplifier will be at the value logic 1 at the output for row[0]. The search data do not match from the store value of row [1], row [2], and row [3], however in the case of row [1], row [2], and row [3], the search data string values do not match with the store value; as a result, the ML [1], ML [2]and ML [3] discharge from initial precharged value to zero value and sense amplifier will be at the value of logic 0.…”

Section: B In Memory Cam Operationmentioning

confidence: 99%

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Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Rajput¹,

Pattanaik²,

Kaushal³

2021

Preprint

0

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The In-Memory Computing (IMC) architecture based on 6T, 8T, 10T SRAM fails under process-variation and suffers from compute-disturb, compute-failure, half-select issue, respectively, which affect the reliability of IMC operation. To overcome these problems, local bit-line sharing Dual-Port 8T (SDP8T) SRAM with Virtual VSS is proposed to improve the stability and energy efficiency of IMC architecture. The decouple read-write path with high-Vth transistor is used to improve the read-margin by 2.11× and reduce the read-energy by 36.35% as compared to Transpose-8T SRAM. The virtual VSS write assist is used in SDP8T SRAM to improve the write-margin by 26.49%, and lower the leakage power by 47.95% as compared to Transpose-8T SRAM. Furthermore, IMC architecture is proposed using SDP8T SRAM. In addition to the SRAM function, SDP8T-IMC architecture performs In-memory Boolean computation(IMBC) operations without compute-disturbance and compute-failure. The remarkable feature of SDP8T-IMC architecture is that it performs IMBC operation on four operands simultaneously using all four bit-line ports in a single cycle, thus doubling the throughput and obtain 11.04 fJ/bit average energy consumption at 1 V supply. The maximum operating frequency of the proposed IMC architecture is 1050 MHz at 1 V. Cumulatively, the proposed SDP8T-IMC architecture has 32.22%, 27.03%, 60.10%, 50.93%, 60.48%, 35.05%, and 65.28% reduction in energy consumption as compared to C6T, 6TCSRAM, 8+T, 8T, 10T, 12T, and 4+2T SRAM based IMC architectures, respectively. Moreover, the proposed IMC architecture is configured as Binary Content Addressable Memory (BCAM) for searching applications which achieves 0.60fJ energy consumption per search/bit at 1 V.

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“…Thanks to the massive data parallelism, ultrahigh internal memory bandwidth, and reduced data movement, IMC brings high performance and energy efficiency. In addition, state-Of-The-Art (SOTA) IMC devices can conduct Boolean functions and addition operations, making them very suitable for accelerating addition-centric CNNs [23], [24], including BWNs and TWNs.…”

Section: Introductionmentioning

confidence: 99%

FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

Zhu,

Duong,

Chen

et al. 2022

Preprint

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Convolutional Neural Networks (CNNs) demonstrate great performance in various applications but have high computational complexity. Quantization is applied to reduce the latency and storage cost of CNNs. Among the quantization methods, Binary and Ternary Weight Networks (BWNs and TWNs) have a unique advantage over 8-bit and 4-bit quantization. They replace the multiplication operations in CNNs with additions, which are favoured on In-Memory-Computing (IMC) devices. IMC acceleration for BWNs has been widely studied. However, though TWNs have higher accuracy and better sparsity, IMC acceleration for TWNs has limited research. TWNs on existing IMC devices are inefficient because the sparsity is not well utilized, and the addition operation is not efficient.In this paper, we propose FAT as a novel IMC accelerator for TWNs. First, we propose a Sparse Addition Control Unit, which utilizes the sparsity of TWNs to skip the null operations on zero weights. Second, we propose a fast addition scheme based on the memory Sense Amplifier to avoid the time overhead of both carry propagation and writing back the carry to the memory cells. Third, we further propose a Combined-Stationary data mapping to reduce the data movement of both activations and weights and increase the parallelism of memory columns. Simulation results show that for addition operations at the Sense Amplifier level, FAT achieves 2.00× speedup, 1.22× power efficiency and 1.22× area efficiency compared with State-Of-The-Art IMC accelerator ParaPIM. FAT achieves 10.02× speedup and 12.19× energy efficiency compared with ParaPIM on networks with 80% sparsity.

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“…Area of various cell normalized with respect to 6T SRAM 2. Number of computation in single cycle 3. Number of cycle require to perform all computation.…”

mentioning

confidence: 99%

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Rajput¹,

Pattanaik²,

Kaushal³

2021

Preprint

0

View full text Add to dashboard Cite

The In-Memory Computing (IMC) architecture based on 6T, 8T, 10T SRAM fails under process-variation and suffers from compute-disturb, compute-failure, half-select issue, respectively, which affect the reliability of IMC operation. To overcome these problems, local bit-line sharing Dual-Port 8T (SDP8T) SRAM with Virtual VSS is proposed to improve the stability and energy efficiency of IMC architecture. The decouple read-write path with high-Vth transistor is used to improve the read-margin by 2.11× and reduce the read-energy by 36.35% as compared to Transpose-8T SRAM. The virtual VSS write assist is used in SDP8T SRAM to improve the write-margin by 26.49%, and lower the leakage power by 47.95% as compared to Transpose-8T SRAM. Furthermore, IMC architecture is proposed using SDP8T SRAM. In addition to the SRAM function, SDP8T-IMC architecture performs In-memory Boolean computation(IMBC) operations without compute-disturbance and compute-failure. The remarkable feature of SDP8T-IMC architecture is that it performs IMBC operation on four operands simultaneously using all four bit-line ports in a single cycle, thus doubling the throughput and obtain 11.04 fJ/bit average energy consumption at 1 V supply. The maximum operating frequency of the proposed IMC architecture is 1050 MHz at 1 V. Cumulatively, the proposed SDP8T-IMC architecture has 32.22%, 27.03%, 60.10%, 50.93%, 60.48%, 35.05%, and 65.28% reduction in energy consumption as compared to C6T, 6TCSRAM, 8+T, 8T, 10T, 12T, and 4+2T SRAM based IMC architectures, respectively. Moreover, the proposed IMC architecture is configured as Binary Content Addressable Memory (BCAM) for searching applications which achieves 0.60fJ energy consumption per search/bit at 1 V.

show abstract

In-Memory Computing: The Next-Generation AI Computing Paradigm

Cited by 18 publications

References 27 publications

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

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