Local Bit-Line Sharing Robust Dual-Port 8T SRAM With Virtual VSS for Energy-Efficient In-Memory Computing Architecture

Abstract

The In-Memory Computing (IMC) architecture based on 6T, 8T, 10T SRAM fails under process-variation and suffers from compute-disturb, compute-failure, half-select issue, respectively, which affect the reliability of IMC operation. To overcome these problems, local bit-line sharing Dual-Port 8T (SDP8T) SRAM with Virtual VSS is proposed to improve the stability and energy efficiency of IMC architecture. The decouple read-write path with high-Vth transistor is used to improve the read-margin by 2.11× and reduce the read-energy by 36.35% as compared to Transpose-8T SRAM. The virtual VSS write assist is used in SDP8T SRAM to improve the write-margin by 26.49%, and lower the leakage power by 47.95% as compared to Transpose-8T SRAM. Furthermore, IMC architecture is proposed using SDP8T SRAM. In addition to the SRAM function, SDP8T-IMC architecture performs In-memory Boolean computation(IMBC) operations without compute-disturbance and compute-failure. The remarkable feature of SDP8T-IMC architecture is that it performs IMBC operation on four operands simultaneously using all four bit-line ports in a single cycle, thus doubling the throughput and obtain 11.04 fJ/bit average energy consumption at 1 V supply. The maximum operating frequency of the proposed IMC architecture is 1050 MHz at 1 V. Cumulatively, the proposed SDP8T-IMC architecture has 32.22%, 27.03%, 60.10%, 50.93%, 60.48%, 35.05%, and 65.28% reduction in energy consumption as compared to C6T, 6TCSRAM, 8+T, 8T, 10T, 12T, and 4+2T SRAM based IMC architectures, respectively. Moreover, the proposed IMC architecture is configured as Binary Content Addressable Memory (BCAM) for searching applications which achieves 0.60fJ energy consumption per search/bit at 1 V.