In‐Memory Binary Vector–Matrix Multiplication Based on Complementary Resistive Switches

Abstract

With artificial neural networks (ANNs) becoming more and more powerful and with the slowdown of complementary metal-oxide-semiconductor (CMOS) scaling, the Von Neumann memory wall is becoming an increasingly prominent problem for ANN hardware systems. [1,2] Large neural networks especially suffer from this because not all computational information necessary can be stored in the cache memory, and costly communication with higher level storage is necessary. [3] In software, techniques such as pruning, weight reuse, or reducing the quantization are used to create less complex but still accurate ANNs. [4] A promising simplification from the hardware perspective is the aforementioned reduction in quantization due to its reduced computational complexity. The number of quantization levels can even go down to the bare minimum of two levels and results in binary neural networks (bNNs) which have been heavily studied in recent years. [5-8] These networks use the values 1 and À1 to encode their weights and activations during the inference step making them the most efficient ANNs possible to compute in hardware. [9] With ongoing improvements in prediction accuracy and the development of new hardware accelerators, these networks are auspicious candidates for computing ANNs on edge devices. Apart from the use of CMOS accelerators, new emerging technologies based on resistive switching devices can play a crucial role in this advancement. [10] These devices can mimic the synaptic weights in ANNs and, configured in a crossbar architecture, enable fast analog computations of vector-matrix multiplications, which are the main operations in ANNs. [11,12] One promising class of resistive switching devices relies on redox reactions and is therefore called redox-based resistive switching devices, also known as redox-based random access memory (ReRAM). [13] They are typically based on metaloxide-metal stacks and can change the conduction through the oxide layer based on electric signals applied to the metal electrodes. These changes in resistance from a high resistive state (HRS) to a low resistance state (LRS) and vice versa originate from ionic movements in the oxide layer and concurrent redox reactions. [14] There are already many realizations of ReRAM crossbar arrays used as accelerators for vector-matrix multiplication. [15-17] One common type uses Kirchoff 's current law to do the computation where the calculation result is encoded in the resulting current. To compute this result, the current has to be sensed, which becomes more difficult the lower the current is. This leads to a trade-off in the circuit design as a lower current reduces the energy consumption. Another commonly used architecture builds up a resistive voltage divider between a sense resistance and the resistive crossbar array. In this architecture, the result of the computation is encoded in the voltage drop of the voltage divider. [18] One design challenge of this architecture is the

Artificial optoelectronic synapse based on spatiotemporal irradiation to source‐sharing circuitry of synaptic phototransistors

“…2,3 These neuromorphic devices can perform vector-matrix multiplication, which is the core computation of machine learning, through analog processing, thus improving power consumption and bandwidth. [4][5][6][7] Artificial synapses featuring synaptic properties such as short-term plasticity (STP), long-term potentiation/ depression (LTP/LTD), and spike-timing-dependent plasticity have been a major component to realize neuromorphic devices. 8 The conductance of artificial synapses can be dynamically modulated by electrical or optical pulses, which are used to achieve a target synaptic weight for neural network computing.…”

Evolutionary Learning of Binary Neural Network Using a TaOx Memristor via Stochastic Stateful Logic

“…Recently, the memristive crossbar array (MCA) has been widely studied as an alternative approach for the binary weight matrix. [6][7][8][9] Because the memristor can serve as nonvolatile data storage in a two-terminal manner, it can increase data density significantly. Also, the MCA can instantly execute a physics-based vector-matrix multiplication via Kirchhoff's law, which enables a fast and energy-efficient inferencing process.…”

Implementation of Highly Reliable and Energy Efficient in‐Memory Hamming Distance Computations in 1 Kb 1‐Transistor‐1‐Memristor Arrays

“…[1][2][3][4][5] As one of the most promising data security techniques, the Hamming distance (HD) computations, that is, the processing of the number of different characters in the corresponding positions between two equal-length binary strings [6] is now being intensively applied in the fields of information security encryption, [7][8][9][10] image search and recognition, [11][12][13] and binary neural networks. [14][15][16][17][18] In-memory computing (IMC) has remarkably enhanced data-intensive applications, reaching beyond the level of von Neumann computing in terms of processing latency and energy efficiency. [19][20][21] Hence, it is imperative to develop a reliable and efficient in-memory HD computational architecture, which has become a surge of research topic for both academic and industrial communities.…”

“…[31] Compared to unipolar devices, the bipolar resistive switching can overcome the reliability issue as reported in prior studies conducted on the HD computations based on the complementary bipolar switches. [14,29,30,[32][33][34][35][36] However, the conductive filament mechanism inevitably leads to a variation of low resistance state (LRS) and high resistance state (HRS). In fact, the accuracy of the HD computations is highly influenced by the fluctuations of the resistance, because the output of the HD computations is determined by the accumulation of the total reading current in a RRAM array.…”

“…In fact, the accuracy of the HD computations is highly influenced by the fluctuations of the resistance, because the output of the HD computations is determined by the accumulation of the total reading current in a RRAM array. [14] Hence, there is a pressing need for the development of highly reliable and energy efficient in-memory HD computation devices based on a bipolar switching mechanism that can continuously adapt to the data processing demand. [1,37] In the present work, to address the aforementioned issues, we demonstrate a new HD computations scheme based on a highperformance 1-transistor-1-memristor (1T1M) arrays architecture.…”