IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions

Abstract

A secure processor requires that no secret, undocumented instructions be executed. Unfortunately, as today's processor design and supply chain are increasingly complex, undocumented instructions that can execute some specific functions can still be secretly introduced into the processor system as flaws or vulnerabilities. To address this problem that may cause potentially serious security breaches, the instruction set architecture (ISA) monitor and secure cache (IMSC) is proposed. As a lightweight solution, IMSC employs an ISA monitor to discover and correct any potential threats imposed by undocumented instructions, and it relies on a secure cache to ensure the credibility of the system. The authors’ case studies have confirmed that IMSC can effectively protect a processor system from being exploited by undocumented instructions and thus provide a trustworthy computing environment, all at low hardware and run‐time costs.

An efficient mining method for DSP undocumented instruction

“…We match this machine code with the fixed values and opcodes in the database○ 2 . Specifically, if any field of h s successfully matches the fixed value in the database, we will further extract and compare the opcode field between the machine code to be tested and the database○ 3 . A successful match indicates that the machine code is legal and can be disassembled, and the analysis of the instructions will be continued.…”

“…Such an important infrastructure also attracts attackers to take advantage of the loopholes to achieve their illegal purposes. Nowadays, the instruction set which serves as a critical interface between processor hardware units and software is no longer reliable [3]. Duflot L. [4] is the first to discover the existence of undocumented instructions in processors.…”