Impurity Distribution in Epitaxial Silicon Films

Thomas, Candice; Kahng, D.; Manz, R. C.

doi:10.1149/1.2425235

Cited by 149 publications

(65 citation statements)

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“…Grossman (10) and Thomas et al. (11,12) have proposed that, in the reversible reaction of silicon tetrachloride and silicon in a hydrogen ambient, a thin surface layer of the silicon substrate is transferred into the gas phase and later redeposited. As a consequence of this, the impurity density distribution at the substrate-epitaxial layer interface will be more 1123 diffuse than predicted by diffusion theory.…”

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confidence: 99%

Epitaxial Growth of Silicon from Dichlorosilane

Lekholm¹

1972

J. Electrochem. Soc.

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Epitaxial silicon has found many important applications in solid-state devices. These applications may be divided into two groups: components that exploit the unique feature of epitaxy to produce layers of any desired doping on higher doped contact regions, and components that have abrupt transitions in the doping profile as an integrated part of the device.In components where sharp steps in the impurity density distribution are required, it is necessary to minimize the Dt product of diffusion coefficient and time in the growth step. Since it is impossible to increase the growth rate above a few #m/rain (and thus decrease time) in the silicon tetrachloride process, the natural solution to this problem is to decrease the growth temperature. This is also a very effective way of decreasing the Dt product because the diffusion coefficient of most impurities in silicon decreases about one order of magnitude for every 100~ decrease in temperature.Of the different methods available for low temperature epitaxial growth of silicon, thermal decomposition of silane has attracted most interest. Growth temperatures as low as 800~ are reported (1). To obtain high growth rates special schemes, such as watercooled reaction vessels, have to be used to avoid gas phase decomposition and fallout of polycrystalline silicon on the wafers. Improved growth techniques have resulted in growth rates of 5 ~m/min at 1000~ (2). Further increase in the growth rate is possible if the hydrogen carrier gas is substituted by helium. Using this scheme, growth rates of 3 ~m/min at 900~ are reported (1).In a production system one must, however, make a choice between the simplicity of the silicon tetrachloride process and the better results (in terms of Dt product) of the more complicated silane process.This paper presents results from epitaxial growth of silicon from dichlorosilane. It allows high growth rates at substantially lower temperatures than silicon tetrachloride. Unlike silane, dichlorosilane is relatively stable in the gas phase and problems with premature gas phase pyrolysis are small or nonexistent.For the experiments described, an epitaxial system with vertical gas flow and a rotating rf-heated carbon susceptor was used. The susceptor diameter is 12.5 cm and is designed to carry seven 11/4 in. diam silicon wafers. The total gas flow in all runs was 27 liters/ min. The system was originally designed to use silicon tetrachloride; however, no alterations were made for these dichlorosilane experiments.The temperature of the silicon wafers was measured with an optical pyrometer or an electro-optic, IR detector and was corrected for emissivity and for absorption losses in the quartz of the bell jar. The gas flow rates were monitored with flowraeters calibrated for the gases used. The thicknesses of the epitaxial layers were determined from infrared interference measurements.Great care was taken to obtain reproducible results from run to run. In order to improve the temperature measurements, the susceptor was etched clean between each experime...

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confidence: 99%

Epitaxial Growth of Silicon from Dichlorosilane

Lekholm¹

1972

J. Electrochem. Soc.

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“…In order to find the carrier concentration depth profiles of the SC and DC heterostructures, we applied the C-V profiling technique at room temperature [23][24][25]. The C-V measurement allows one to measure the carrier concentration, N C-V , as a function of depth, z, where [24],…”

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confidence: 99%

Current-Transport Mechanisms in the AlInN/AlN/GaN single-channel and AlInN/AlN/GaN/AlN/GaN double-channel heterostructures

et al. 2013

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Current-transport mechanisms were investigated in Schottky contacts on AlInN/AlN/GaN single channel (SC) and AlInN/AlN/GaN/AlN/GaN double channel (DC) heterostructures. A simple model was adapted to the current-transport mechanisms in DC heterostructure. In this model, two Schottky diodes are in series: one is a metal-semiconductor barrier layer (AIInN) Schottky diode and the other is an equivalent Schottky diode, which is due to the heterojunction between the AlN and GaN layer. Capacitance-voltage studies show the formation of a two-dimensional electron gas at the AlN/GaN interface in the SC and the first AlN/GaN interface from the substrate direction in the DC. In order to determine the current mechanisms for SC and DC heterostructures, we fit the analytical expressions given for the tunneling current to the experimental current-voltage data over a wide range of applied biases as well as at different temperatures. We observed a weak temperature dependence of the saturation current and a fairly small dependence on the temperature of the tunneling parameters in this temperature range. At both a low and medium forward-bias voltage values for Schottky contacts on AlInN/ AlN/GaN/AlN/GaN DC and AlInN/AlN/GaN SC heterostructures, the data are consistent with electron tunneling to deep levels in the vicinity of mixed/screw dislocations in the temperature range of 80-420 K.

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“…Using a model which takes into account the arsenic incorporation based on trapping of adsorbed atoms on the growing surface Wang et al 9 solved a first-order differential equation for the impurity concentration with solution [1] where ND(x) is the doping concentration, N ~ is the initial ,surface concentration of arsenic adjacent to the buried layer regions, f is the trapping factor, Zm is the characteristic decay length, and xB~ is the position where the profile reaches the background concentration (CBG)- Figure 3 shows the resulting doping profiles, as measured by spreading resistance profiling (SRP), in the off buried layer region approximately 20 ~m from the buried layer edge. These layers grew at three different growth rates with the prebake temperature fixed at 1000~ We held the growth time constant at 5 rain for each of the profiles depicted in Fig.…”

Section: Resultsmentioning

confidence: 99%

Suppression of Arsenic Autodoping with Rapid Thermal Epitaxy for Low Power Bipolar Complementary Metal Oxide Semiconductor

King

Johnson

Chiu

et al. 1995

J. Electrochem. Soc.

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Scaled bipolar transistors for bipolar complementary metal oxide semiconductor (BiCMOS) integrated circuits require low collector-substrate capacitance in order to minimize power consumption. The unintentional incorporation of dopant into a growing epitaxial layer, known as autodoping, can affect the ultimate lower limit of the collector-substrate capacitance. In this work, we studied the effects of epitaxial layer growth rate, arsenic-buried layer implant dose, and pre-epitaxia] bake temperature on autodoping using rapid thermal epitaxy (RTE). To begin, we experimented with the buried layer implant dose to check its affect on lateral autodoping. The amount of autodoping increased when the buried layer implant dose increased, confirming the source of the arsenic autodoping as the buried layer. Also, in contrast to data from conventional reactors, we found the peak interface concentration and integrated dose in regions adjacent to the buried layer to be linearly dependent on the growth rate (i.e., low growth rates trap less arsenic at the substrate/epi layer interface) for all growth rates studied. Next, by adjusting the prebake temperature over a range from 800 to I050~ without changing the growth conditions, we first observed a rise in autodoping with temperature to 950~ at which point the incorporated autodoping dose and peak concentration began to fall. Through simulation of the evaporated arsenic from the buried layer and data for arsenic desorption from the silicon surface, we explain this behavior. Finally, using the data gathered on the autodoping characteristics of RTE, we show a process using two growth rate steps and a low temperature prebake step which completely eliminates the lateral autodoping peak. Using this new growth process, epitaxial silicon films over arsenic-doped buried layers for low power BiCMOS are possible.

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Impurity Distribution in Epitaxial Silicon Films

Cited by 149 publications

References 1 publication

Epitaxial Growth of Silicon from Dichlorosilane

Epitaxial Growth of Silicon from Dichlorosilane

Current-Transport Mechanisms in the AlInN/AlN/GaN single-channel and AlInN/AlN/GaN/AlN/GaN double-channel heterostructures

Suppression of Arsenic Autodoping with Rapid Thermal Epitaxy for Low Power Bipolar Complementary Metal Oxide Semiconductor

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