2007 International Symposium on Industrial Embedded Systems 2007
DOI: 10.1109/sies.2007.4297313
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Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis

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Cited by 5 publications
(5 citation statements)
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“…• Furthermore, the Cheddar project has also contributed in many research projects related to model driven engineering or real-time system performance analysis (Gilles and Hugues 2008;França et al 2007;Hugues et al 2008;Revest et al 2007;Nemer et al 2007). For example, in the context of the European IST ASSERT project, Hugues et al (2008) have shown that Cheddar can be used in a process in which a real-time system is modelled with AADL and verified by Cheddar or CPN-AMI (Hamez et al 2006 These first encouraging experiments may lead to numerous future works.…”
Section: Discussionmentioning
confidence: 99%
“…• Furthermore, the Cheddar project has also contributed in many research projects related to model driven engineering or real-time system performance analysis (Gilles and Hugues 2008;França et al 2007;Hugues et al 2008;Revest et al 2007;Nemer et al 2007). For example, in the context of the European IST ASSERT project, Hugues et al (2008) have shown that Cheddar can be used in a process in which a real-time system is modelled with AADL and verified by Cheddar or CPN-AMI (Hamez et al 2006 These first encouraging experiments may lead to numerous future works.…”
Section: Discussionmentioning
confidence: 99%
“…• An actual formula is being generated (lines [14][15][16][17]. This formula is passed to and processed by a SAT solver (lines [18][19][20], which determines it to be satisfiable. As reported in line 21, the SAT solver spent approximately 4 ms to compute a model.…”
Section: C2mentioning
confidence: 99%
“…In the following, we are going to demonstrate how to apply the test suite generation functionality in CBMC. The program pid.c in Listing 11 is an excerpt from a realtime embedded benchmark PapaBench [19], and implements part of a fly-by-wire autopilot for an Unmanned Aerial Vehicle (UAV). We have adjusted it slightly for our purposes.…”
Section: Test Inputsmentioning
confidence: 99%
“…Some WCET estimation techniques pay attention to the effect of private caches on WCETs. In [31], when analyzing the timing behavior of a task, Nemer et al take into account the set of memory blocks that has been stored in the instruction cache (by the execution of previous tasks on the same core) at the beginning of its execution. Similarly, Potop-Butucaru et al [39], assuming task mapping on cores known, jointly perform cache analysis and timing analysis of parallel applications.…”
Section: Related Workmentioning
confidence: 99%