Improving the Speed of Parallel Decimal Multiplication

Jaberipur, Ghassem; Kaivani, Amir

doi:10.1109/tc.2009.110

Cited by 67 publications

(33 citation statements)

References 24 publications

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“…We can generate a test counter waveform from the Project New Source menu of ISE and it will support in setting up the simulation. Once we simulate our design and feel it is function properly, then we can move on to generating the data needed to essentially program the objective tool with our system design [6].…”

Section: Analysis and Implementationmentioning

confidence: 99%

Low Power Dissipation Binary to BCD Converter for Multi-Operand B/D Adder

Sharma¹,

Soni²

2017

IJCA

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The main objective to design this paper to increasing importance of commercial application , economic and Internet-based applications the decimal adder provide useful statistic in formative each adder's performance and scalability. There is a new interest in providing hardware support to handle decimal data. In this paper, a new architecture binary to BCD converter for multi-operand addition implement of binary coded decimal (BCD) operands, which is the core of high speed multi-operand adders. the proposed Simulation results show that the add-3 digit BCD adder achieves an improvement of 70 % in delay and area and it consume very less power. The 2,4,8,16-digit BCD lookahead adder shown to achieve at least 90 % faster than the accessible ripple carry one. The coding will be written in VHDL and verified in I-Sim. After the coding the synthesis of the code was performed using Xilinx-ISE. Synthesis tool ISE 14.7.

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Section: Analysis and Implementationmentioning

confidence: 99%

Low Power Dissipation Binary to BCD Converter for Multi-Operand B/D Adder

Sharma¹,

Soni²

2017

IJCA

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“…That track of work also started by fixed point combined units [43,44] and then floating point combined units followed [45]. Other researchers focused on improving the speed of parallel multiplication [46] including the use of redundant representations [47,48].…”

Section: Specific Designsmentioning

confidence: 99%

Decimal Floating Point Number System

Fahmy

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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“…In [8], speed optimized parallel multiplier algorithm generation is presented and in this algorithm partial product reduction is achieved by vertical compression slice (VCS). In [9], improvement of speed of parallel decimal multiplication using double BCD multiple computation approach, for partial product generation is presented. In [10], high speed multiplication algorithm is presented in which both multiplicand and multiplier are redundant binary integers used to generate partial products.…”

Section: Related Workmentioning

confidence: 99%

Area Efficient High Speed and Low Power MAC Unit

Kalaiselvi¹,

Mangalam²

2013

IJCA

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With the growing importance of electronic products in day-today life, the need for portable electronic products with low power consumption largely increases. In this paper, an area efficient high speed and low power Multiply Accumulator unit (MAC) with carry look-ahead adder (CLA) as final adder is being designed. In the same MAC architecture design in final adder stage of partial product unit the carry save adder(CSA), carry select adder(CSLA) and carry skip adder(CSKPA) are also used instead of CLA to compare the power and performance. These MAC designs were simulated and synthesized using Xilinx 8.1. The simulation result shows that the MAC design with CLA has area reducing by 16.7%, speed increase by 1.95% and the consumed power reducing by 0.5%.

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Improving the Speed of Parallel Decimal Multiplication

Cited by 67 publications

References 24 publications

Low Power Dissipation Binary to BCD Converter for Multi-Operand B/D Adder

Low Power Dissipation Binary to BCD Converter for Multi-Operand B/D Adder

Decimal Floating Point Number System

Area Efficient High Speed and Low Power MAC Unit

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