Improving the RF performance of 0.18 /spl mu/m CMOS with deep n-well implantation

Su, Jun-Ming; Hsu, Heng-Ming; Wong, Shyh-Chyi; Chang, Chun‐Yen; Huang, Tiao–Yuan; Sun, J.Y.-C.

doi:10.1109/55.954918

Cited by 26 publications

(5 citation statements)

References 12 publications

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“…It is found that deep N-well (DNW) 7,10) isolation can greatly suppress the standby leakage current of a TVS device, as revealed in Fig. 5.…”

Section: Measurement Results and Discussionmentioning

confidence: 91%

“…The experiment is realized with a standard 0.18 mm process; the doping profiles of the P-well and deep N-well are the same as listed in a previous report. 7) The shallow trench isolation (STI) region defines the distance between diodes, which can affect the overall breakdown characteristics of this device. The STI depth is about 0.4 mm.…”

Section: Structure Of Low-capacitance Back-to-back Diodementioning

confidence: 99%

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Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor

Dai

Peng

Chen

et al. 2010

Jpn. J. Appl. Phys.

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We establish explicit relations between the residual entropy of the onedimensional Ising chain with a nearest-neighbour ferromagnetic and & th-neighbour antiferromagnetic interaction, and the residual entropies of the one-dimensional king chain with many-neighboured antiferromagnetic interactions in the corresponding maximum critical fields. The obtained results are, in particular, relevant to the chains that appear in the axial next-nearest-neighbour Ising model.The axial next-nearest-neighbour Ising (or ANNNI) model in d dimensions consists of (d -1)dimensional layers of spins with nearest-neighbour ferromagnetic coupling, Jo > 0, within layers but competing ferromagnetic, J 1 , and antiferromagnetic, J2 < 0,

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“…It is found that deep N-well (DNW) 7,10) isolation can greatly suppress the standby leakage current of a TVS device, as revealed in Fig. 5.…”

Section: Measurement Results and Discussionmentioning

confidence: 91%

Section: Structure Of Low-capacitance Back-to-back Diodementioning

confidence: 99%

Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor

Dai

Peng

Chen

et al. 2010

Jpn. J. Appl. Phys.

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“…As can be seem, for the five single-gate-finger nMOSFETs with gate-width of 20, 40, 80, 120, and 160 mm, respectively, f max decreases with the increase of gate-width, which is consistent with the trend predicted by eq. (8). Besides, though an increase of gate-width enhances g m , however, C g .…”

Section: Impact Of Distributed R G On F T and F Maxmentioning

confidence: 94%

“…Deep n-well implantation was adopted to improve the RF performances with negligible dc disturbance. 8) …”

Section: Device Architecturementioning

confidence: 99%

Uniformly Distributed Wideband Metal–Oxide–Semiconductor Field-Effect Transistor Model for Complementary Metal–Oxide–Semiconductor Radio-Frequency Integrated Cirsuits Applications

Liang¹,

Tsou²,

Lin³

et al. 2008

jjap

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In this paper, a uniformly distributed wide-band metal-oxide-semiconductor field-effect transistor (MOSFET) model constructed by several same unit cells in parallel is presented. The kink phenomenon of scattering parameter S 11 due to the distributed gate-resistance of MOSFETs can be fitted well by this model. Good agreement between the measured and modeled results of scattering parameters S 22 , current gain H 21 , and unilateral gain U are also demonstrated. In addition, the impact of distributed gate-resistance on cut-off frequency ( f T ) and maximum oscillation frequency ( f max ) performances of single gatefinger MOSFETs with large gate-width of 20, 40, 80, 120, and 160 mm are quantitatively characterized and analyzed.

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“…The geometric mean of the STI thickness (t STI = 220 nm, lower boundary [7], [11], [12]) and maximum MOSIS Scalable CMOS well thickness (750 nm, upper boundary [13]) gives an estimate for t Well of 406 nm. t DNW is estimated to be 1.13 µm based on the PW and DNW ratio (2.78) from [14]. Table I shows the resulting estimated η A .…”

Section: Responsivity and Frequency Response Analysismentioning

confidence: 99%

Characterisation of Photodiodes in 22 nm FDSOI at 850 nm

Bakker,

Alink,

Schmitz

et al. 2023

ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference (ESSDERC)

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We present the analysis and measurement results of photodiodes (PDs) fabricated in 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology at a wavelength of 850 nm. To the best of our knowledge this is the first paper to give detailed information about PDs in 22 nm FDSOI. FDSOI has the unique opportunity to place a PD in SOI, which is potentially very fast, on top of bulk devices such as PNP-transistors for temperature sensors. Its measured responsivity is 4 µA/W at a bandwidth (BW) of 3.4 GHz. Several bulk PDs, including PW/NW/DNW, PW/DNW/PSUB, and NW/PSUB have also been characterised. They have responsivities between 6 mA/W and 207 mA/W and BWs between 23 MHz and 5.8 GHz. 22 nm FDSOI shows potential for fully-integrated high-speed optical receivers, as it combines ∼90 nm bulk CMOS PD performance with 22 nm RF and digital processing capabilities on a single die.

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Improving the RF performance of 0.18 /spl mu/m CMOS with deep n-well implantation

Cited by 26 publications

References 12 publications

Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor

Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor

Uniformly Distributed Wideband Metal–Oxide–Semiconductor Field-Effect Transistor Model for Complementary Metal–Oxide–Semiconductor Radio-Frequency Integrated Cirsuits Applications

Characterisation of Photodiodes in 22 nm FDSOI at 850 nm

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