Improving the power-performance of multicore processors through optimization of lithography and thermal processing

Gabor, Allen H.; Brunner, Tim; Bukofsky, S.; Butt, S.; Clougherty, F.; Deshpande, Sadanand V.; Faure, Tom; Gaidai, Oleg; Greene, Kevin; Johnson, Jeff; Le, Nghia; Lindo, P.; Mahorowala, Arpan P.; Nam, Hyungju; Onsongo, D.; Poindexter, D.; Rankin, Jed; Rohrer, Norman J.; Stiffler, S. R.; Thomas, A.; Utomo, H.

doi:10.1117/12.711750

Cited by 4 publications

(2 citation statements)

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“…With the advent of electronic testing, there are new opportunities to communicate with designers and create circuit layout patterns with enhanced and parameter isolating response. Solutions can be pursued across disciplines rather than within disciplines by providing collaborative frameworks to view the same information in terms of concepts for which they have an existing intuition (layout, BSIM, SPICE) [59]. Layouts that are hyper-sensitive can also be created such as the gate and interconnect layouts in Figure 12 that react to focus.…”

Section: Growth Areas For Simulationmentioning

confidence: 99%

If it moves, simulate it!

Neureuther

2008

Optical Microlithography XXI

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In the last 35 years modeling of projection printing has undergone many paradigm shifts in physical models, computational engines, algorithms and opportunities. The trigger event for the first quantitative positive resist Dill model was the development and application of automated thin-film measurement equipment. The use of partial coherence which helps imaging also complicates the understanding and necessitates the use of simulation to guide lithography practice. Simulation has also played an important role in discovery (intensity imbalance in phase-shifting masks), invention (self-interferometric mask monitors) and creation of analysis techniques (first-cut accurate fast-CAD). The current challenges and growth areas for simulation include calibration, synergy with metrology, electronic self-testing and linking circuit design and fabrication.

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Section: Growth Areas For Simulationmentioning

confidence: 99%

If it moves, simulate it!

Neureuther

2008

Optical Microlithography XXI

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“…The need to complement and manage traditional and still critical metrology techniques with parametric in-line, in-die measurement which correlates directly to product performance and ultimately final bin-yield has been recognized [3]. PBM accelerates the gathering and availability of the current critical measurements of product representative [4] RO-type test structures in the scribe and die [5] from early stages of product development and continuously throughout the manufacturing process steps and phases.…”

Section: Introductionmentioning

confidence: 99%

Non-Contact, Pad-less Measurement Technology and Test Structures for Characterization of Cross-Wafer and In-Die Product Variability

Steinbrueck

Vickers

Babazadeh

et al. 2009

2009 IEEE International Conference on Microelectronic Test Structures

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Monitoring and controlling cross-wafer and in-die variability has been recognized as the dominant and escalating factors for the successful commercialization of modern-day integrated circuit products utilizing advanced semiconductor manufacturing [1,2]. In this paper we present a Performance Based Metrology (PBM), a measurement technology for closing the information gap between the design, process integration, and manufacturing groups with respect to accounting for variability. PBM enables the "porting" of scribe-like and end-of-line contact tested measurements to within the product die active area to it provide the capability to significantly reduce the cycles of learning to obtain relevant and key process, device, and product metrics. This product-relevant information can then be used for process monitoring and control, performance optimization, and to enhance early bin-yield predictability. The technique would reduce or eliminate the need for send-ahead test wafers and other "disruptive" measurements by making possible in-die, non-contact characterization of product performance monitors and devices. We describe the in-line measurement system and review the design and implementation considerations for the non-contact test structures incorporated on product wafers. Experimental results from PBM measurements on several generations (90, 65, and 45nm) of bulk-Si and SOI product wafers and devices are presented to illustrate the capabilities of the technique.

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